Revolutionizing Interconnect Performance and Reliability Monitoring in a Chiplet based System-In-Package.pdf

1、Revolutionizing Interconnect Performance and Reliability Monitoring in a Chiplet based System-In-PackageChipletsRevolutionizing Interconnect Performance and Reliability Monitoring in a Chiplet based System-In-PackageWalter Ofer Abramsohn,Director PMM,ProteanTecsNir Sever,Director Business Developmen

2、t,proteanTecsMore Than MooreOvercome reticle size limitations for large devicesImprove yield:Yield goes down exponentially with size but with tiling,it is linearAllow hybrid devices:Each IC in a SiP can be manufactured at a different process:CPU/GPU/NPU/TPU on latest CMOS technologyDRAM on DRAM proc

3、essWireless/RF on Analog RF processSupport“economies of scale”with ChipletUses the same building block multiplied according to application instead of multiple designsEfficient interconnect is key for success!Different Tec hnologies C om m on P roblem sPhysical Interconnect TechnologiesSubstrate Tech

4、nologiesSilicon InterposerOrganic SubstrateSerialParallelImages sources:https:/doi.org/10.3390/app10041292https:/ ReliabilityVoids and cracksTSV ReliabilityPartial fillCopper plating crackingVia wall delaminationLane Trace ReliabilityBridge shortsDriver and ReceiverParametric variationAging(driver w

5、eakening,VREF shift,etc.)Intel:The problem is real!Sreejit Chakravarty,Intel,OCP ODSA Project Call-July 8th,2022Challenges for ChipletsTodays Problem:Limited coverage for Chiplet KGD(Known Good Die)Known defect modes related to assembly process may cause poor yield1000s of D2D connections not evalua

6、ted until system testNo test access to D2D interface at SiPlevelExisting test methods limited to Pass/Fail with low resolution,only is Test modeNo in-context,in-field,in-mission mode monitoringSystem in Package(SiP)Interface available at packageChipletDice and Package AssemblyPkg Test EVB/SLT Test P