1A-201_DPUs in Open Infrastructure Deployments-Canonical.PPTX

1、DPUs in OpenInfrastructure DeploymentsFrode NordahlSenior EngineerCanonical Ltd.San Jose,CA April 26-28,2022SmartNIC vs.SmartNIC DPU disambiguationDPU key takeaways,control plane challengesAuto-discovery,PCI(e)VPDOVN VIF Plug Provider framework and OVN VIFUpstream status/availability2San Jose,CA Apr

2、il 26-28,2022SmartNICsAn overloaded termSome classifications include:Packet processing flow:Off-path SmartNICsOn-path SmartNICs Hardware design:ASIC-basedFPGA-based We will focus on off-path SmartNICs and DPUs3San Jose,CA April 26-28,2022Off-path SmartNICOff-path SmartNIC4NICNIC SwitchASIC/FPGAInter

3、nal CPUsFirmwareOVS System Datapathovs-vswitchdP0P1User spaceHost kernelovsdbHostProcessbond0HW LAGAdd-in CardHardwareVF0VF1OVNcontrollerovs-tcuplink 0uplink 1offloadVF driversPF driverswitchdevVF1repVF0repbr-intbr-bond0PCIeSan Jose,CA April 26-28,2022Off-path SmartNICOff-path SmartNIC DPUNIC Switch

4、ASIC/FPGAInternal CPUsFirmwareuplink 0uplink 1ovs-vswitchdP0User spaceHost kernelovsdbVF1repVF0repbr-intHostProcessAdd-in CardHardwareovs-tcOVNcontrollerbond0HW LAGP1No networking agentsDedicated:-CPU-RAM-Kernel-Flash-PCIe ComplexPF0VF0VF1DPU KerneloffloadOVS systemDatapathPF driver(no eswitch)NIC d

5、riverswitchdevVF driverDPU UserspacePCIe 1PCIe 2br-bond0San Jose,CA April 26-28,2022DPU:key takeawaysData Processing Unit(DPU)Embedded system:dedicated CPU,NIC and other componentsNIC is integrated with the main board using an I/O interconnect(e.g.PCIe)NIC is shared by dedicated CPU and host CPU via

6、 separate I/O hierarchiesOff-path architecture:Slow path:packets flow via NIC cores OVS system datapath(offload via tc)OVS+DPDK(offload via rte_flow)Fast path:direct flow via ASIC to the destination bypassing NIC cores6San Jose,CA April 26-28,2022DPU:Control Plane ChallengesMany infra projects expec