Hot Chips 2022 CXL MemoryChallenges.pdf

1、CXL Memory ChallengesAugust 21,2022Prakash Chauhan,Meta&Mahesh Wagh,AMDAMD Official Use Only Memory trends and challenges Cost,bandwidth,capacity CXL enabled solutions heterogeneous,tiered,cost and performance optimized Evolution of CXL attached memory Simple expanders-interleaved expanders-pooled m

2、emory-FAMAI/ML specific topologies CXL attached memory challenges Tiered memory performance making it transparentDeployment challenges-RAS,telemetry,servicing,securityAgenda8/17/222Copyright CXL Consortium 2022|Hot Chips 2022 CXL Tutorial AMD Official Use OnlyMemory an increasing fraction of system

3、sostMemory Price(cost/bit)flat due to scaling challengesIncreasing core counts and new workloads driving memory demandIncreased Capacity Increased BandwidthServer Memory-Challenging Trends8/17/223Data Source:De Dios&AssociatesCopyright CXL Consortium 2022|Hot Chips 2022 CXL Tutorial AMD Official Use

4、 OnlyAdding DDR channels to CPU for bandwidth and capacityLarge CPU socketsCost,ReliabilityPCB layer countAdditional layer per channelBoard form-factorDifficulty fitting in standard widthsIncreasing data rates for bandwidthPCB technologyBack-drill,SMT connectors,blind viasEqualization circuitsComple

5、xity,cost added to both ends1DPC Capacity/Granularity IssuesSystem Level Challenges8/17/224Confidential|CXL Consortium 2022AMD Official Use Only A common,standard interface for many types of memory Enables system flexibility to make use of different media characteristicspersistence,latency,BW,endura

6、nce,etc Enables usage of heterogeneous memory tiers Differential signallingCXL:a media-agnostic memory interface8/17/225DDR3/4/5 DRAMLPDDR3AMPM ComponentMedia ControllerCXL Memory ExpanderCXLDDR3/4/5 DRAMLPDDRDRAMPM ComponentMedia ControllerCXL Memory ExpanderCXLMedia ControllerCXL Memory ExpanderCX