Hot Chips 2022 CXL3 Fabric Intro and use cases.pdf

1、CXL3 Fabric Introduction and use cases August 21,2022Tony Brewer,Micron&Nathan Kalyanasundharam,AMDCopyright|CXL Consortium 2022-Hot Chips 2022-CXL Tutorial .Motivation&Use Cases Why CXL 3.0 Fabric Fabric Basics and Scope Port Based Routing GFAM Device Transaction Flows Host Address Map Address Inte

2、rleaving Device Media Partitions GFAM Device Media Access Protection SummaryAgenda8/21/20222Copyright|CXL Consortium 2022-Hot Chips 2022-CXL Tutorial .Explosive data growth Data stored and analyzed continuously Data volume and velocity demand large clusters for timely analysis Significant power to m

3、ove and copy data There is a need for an efficient low latency and high bandwidth solution which minimizes data movementCXL3 Fabric-Motivation8/21/20223Explosive growth of data and applicationsDATACOMPUTEHPC,AI&HPDASocial mediaHealth Smart citiesIOTCopyright|CXL Consortium 2022-Hot Chips 2022-CXL Tu

4、torial .CXL3 Fabric Use Case Topology8/21/20224Tightly coupled clusterGlobal Shared MemoryGroupCompute Node0DomainLocal CXLMemCompute Node1DomainLocal CXLMemCompute Node2DomainLocal CXLMemCompute NodeNDomainLocal CXLMemCXL Switch ComplexGFAM0GFAM1GFAMxS1S0DramDramS1S0DramDramS1S0DramDramS1S0DramDram

5、NICNICCopyright|CXL Consortium 2022-Hot Chips 2022-CXL Tutorial .Local ScopeDram on the Motherboard100 nsSystem ScopeLocal CXL mem within the Chassis200nsRack ScopeDisaggregated global memory within the Rack=FabricBase&HPA=FabricLimit&V)if(Intlv=0)DPID=DPID/IX;else IntlvMask=(1 (8+Gran)&IntlvMask;IX

6、2=DPID/IX+Way;DPID=FASTIX2.DPID;else HDM/MMIO/System DRAM decode pathReq(DPID,SPID,HPA)Fabric Address Segment Table(FAST)Power-of-two entries x 21 bitsSegment size max=8TB,min=64GB DPID11:0Intlv3:0VDPID11:0Intlv3:0VIX1From Host or Peer DeviceIX2DPID/IX11:0DPID/IX11:0Gran3:0Gran3:0Interleave DPID Tab