Aquabolt PIM 作为 GPU-PIM 协同设计的画布.pdf

1、Mircea R.StanAquabolt PIM as Canvas for GPU-PIM Co-DesignAquabolt PIM as Canvas for GPU-PIM Co-DesignMircea R.StanModern workloads(ML,graph,DB)demand more capacity+bandwidthMemory wall limits efficiencyNeed for Processing in Memory(PiM)/Processing near Memory(PnM)Several commercial Pim/PnM platforms

2、 e.g.Samsung Aquabolt(HBM2-PiM)OneMCC:opens up software/system design for PiMPIMSimulator can also be used for hardware/architecture exploration!Motivation:Breaking/Lowering the Memory Wallhttps:/ as canvas for architectural explorationExample enhancement:Network-on-Memory(NoM)work in progressAnothe

3、r example enhancement:GPU+PiM Co-DesignIMPRINT:Indirect addressing in PiM-enabled HBMOptimized GPU-PiM interaction for ML workloadsEnergy savings+new algorithm opportunities Higher GPU performance with PiM-enabled HBMLower host-to-memory bandwidth demandReduced energy consumptionPath to deploy new a

4、lgorithmsIMPRINT:Indirect Addressing with GPU-hosted HBM-PiMGiven advantages of PIM and feasibility of Aquabolt style of PIM,how can we extend the use of PIM besides standard matrix multiplication and vector addition?One crucial mechanism is being able to work with pointers in memory which means ena

5、bling in-memory virtual-to-physical address translationExtends Aquabolt-style PIM to support indirect addressingEnables in-memory pointer-based operationsJEDEC-compliant and host-transparentGPU/PiM co-design ArchitectureAquabolt-PiM device as memory(as opposed to peripheral)It does not disturb the k

6、ey components such as subarray and bankIt does not require any modification on the host side memory controllers and is still JEDEC-compliantJin Hyun Kim et al.2022.Aquabolt-XL HBM2-PIM,LPDDR5-PIM with in-memory processing,and AXDIMM with acceleration buffer.IEEE Micro 42,3(2022),2030.Sukhan Lee et a