基于芯片组的封装内测试.pdf

1、Speakers:Mike Bartley Alpinum,Boon Chong Ang Intel Contributors:Mike Bartley Alpinum,Boon Chong Ang IntelCorporation,Anand Muthaiah and Yogan Senthilkumar Tessolve,Madhumita Sanyal Synopsys,Rajesh Pendurkar CadenceJames Wong Palo Alto ElectronOpen Possibilities.D2D Chiplet Based SiPTesting Challenge

2、s andSolutionsOutlineOpen Possibilities.Chiplet Test ProblemDFT StrategiesSystem Level and Functional Test Known Good Die(KGD)Testing Test CostTest StandardsProblem statementOpen Possibilities.Multi-die designs are growingOne bad die can cause the whole package to failChallenges in chiplet testing:D

3、FT Standard(Chiplets come from different vendors)Structural Defect Coverage of the individual chipletsStandards InteroperabilityKnown Good Die(KGD)Known Good Stack(KGS)ArchitectureHierarchical Test Architecture including RepairIndividual Chiplets Test data to be available for the final product compa

4、nyFunctional TestReuse of chiplet level tests at System Level(SLT)Use Case Scenarios;Varying Load conditionsChiplet Based SiPsOpen Possibilities.Source:D2D Chiplet InterfaceTestingStatus of Chiplet TestExisting example solution for chiplet testIEEE P1838+1149.1Scan traffic over Native PCIe/USB proto

5、colMuxed with PCIe/USB/other HSIO phyDirect IOs through active interposer with isolation modeOpen Possibilities.Source:D2D Chiplet InterfaceTestingDesign for Test(DFT)StrategiesDesign for Test(DFT):These are Structured TechniquesScan&ATPG(Automatic Test Pattern Generation)Controllability/Observabili

6、tyMemory/Logic BIST(Built In Self-Test)Hierarchical TestIEEE 1149.X Boundary Scan StandardIEEE P1500 Standard for Embedded CoresIEEE 1687 for Embedded InstrumentsIEEE 1838 3D test architectureDesign for Test(DFT)TechniquesUpfront Investment not an OverheadTest Standards help reduce cost by mandating