009-毛海雪.pdf

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1、Creating Custom RISC-V Processors Using ASIP Design ToolsAugust 22,2024 A Post-Quantum Cryptography Case Study毛海雪,新思科技解决方案事业部,资深应用工程师 2024 Synopsys,Inc.2Problem Statement:RISC-V ExtensibilityISA customization&exten-sibility drive RISC-V adoptionX32i32DM8/16/32bX32i32ALUMPYDIVAGUFIX_MPYButter-flyThis

2、 results in ASIPs with a RISC-V baseline ISAChallenges Better power,performance&area(PPA)Preserve RISC-V compatibility:Execute SW code&libraries Reuse HW peripheralsthat have been designed for general-purpose RISC-VWhich extensions are best for the target application domain?How to obtain a high-qual

3、ity SW Development Kit(SDK),including an optimizing compiler?How to obtain a reliable RTL implementation with excellent PPA?How to verify the design?2024 Synopsys,Inc.3Agenda Synopsys ASIP Designer introduction a processor/DSP/accelerator development infrastructure Synopsys ASIP Designer RISC-V offe

4、ring RISC-V example processor models Synopsys RISC-V extension support simple and large-scale extensions Case Study An ASIP for Post-Quantum Cryptography 2024 Synopsys,Inc.4Synopsys ASIP Designer introductionA Processor/DSP/Accelerator Development Infrastructure 2024 Synopsys,Inc.5ASIP DesignerYour

5、Processor ModelSDKRTLOptimizeExplore Industrys leading tool for creating Application-Specific Instruction-Set Processors(ASIPs)Language-based description of ISA provides full architectural flexibility Automatic generation of professional software development kit(SDK)Automatic generation of synthesiz

6、able RTL and debug infrastructure Accelerated verification and virtual prototyping Integrated with Synopsys Reference Design&Verification Flows Increased engineering productivity More than 2 dozen example models included to accelerate engineering productivity From microprocessors,DSPs,vector process