Session 37Design-Technology Optimization and Digital Accelerators.pdf

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1、Session 37 Overview:Design-Technology Optimization and Digital Accelerators DIGITAL CIRCUITS SUBCOMMITTEEThis session presents eight papers that push the boundaries of digital circuit techniques for design-technology optimization,domain-specific computing and digital accelerators,aiming to enhance e

2、nergy efficiency,system performance,and application-specific capabilities.The first paper explores design-technology co-optimization(DTCO)for an industrial processor design,and the second paper presents a chiplet solution for networks-on-textiles with system-on-chip and networking chiplets.The third

3、 paper demonstrates a compute-in-memory(CI M)-based microprocessor utilizing embedded MRAM for neural network inference,and the fourth paper reports a reusable active TSV-interposer with programmability.The fifth paper introduces a complete KSAT solver that achieves 100%solvability or proves unsatis

4、fiability,and the sixth paper showcases a diffusion accelerator leveraging SRAM CI M and eDRAM storage.The seventh paper highlights a GPS acquisition accelerator designed with energy-accuracy-driven optimization and computing,and the eighth paper presents a low-power keyword spotting system featurin

5、g on-chip training for accented users.Session Chair:Jae-sun Seo Cornell Tech,New York,NY Session Co-Chair:Mahmut Ersin Sinangil NVI DI A,Santa Clara,CA 604 2025 I EEE I nternational Solid-State Circuits ConferenceISSCC 2025/SESSION 37/DESIGN-TECHNOLOGY OPTIMIZATION AND DIGITAL ACCELERATORS/OVERVIEW9

6、79-8-3315-4101-9/25/$31.00 2025 I EEE1:30 PM 37.1 IBM Telum II Processor Design-Technology Co-Optimizations for Power,Performance,Area,and Reliability David Wolpert,I BM,Poughkeepsie,NY I n Paper 37.1,I BM and University of Bonn present design technology co-optimization for the 8-core 5.5GHz I BM Te