Session 22Memory Interface.pdf

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1、Session 22 Overview:Memory Interface MEMORY SUBCOMMI TTEESK hynix and Seoul National University present PAM3 GDDR7 interf aces that can achieve 42Gb/s:SK hynix describes a DFE which provides f eedback within 1UI,and Seoul National University describes a clock-ref erred transceiver technology.Hanyang

2、 University and Korea University introduce PAM4 interf aces:Hanyang University introduces a 32-50Gb/s transmitter that includes a ZQ-based FFE,and Korea University introduces a 32Gb/s single-ended receiver that includes a capacitive-f eedback equalizer.In addition,Seoul National University presents

3、a low-power and low-jitter quadrature-clock generator f or high-bandwidth HBMs.Session Chair:Dongkyun Kim,SK Hynix,Icheon,Korea Session Co-Chair:Hidehiro Shiga KIOXIA,Yokohama,Japan 392 2025 IEEE International Solid-State Circuits Conf erenceI SSCC 2025/SESSI ON 22/MEMORY I NTERFACE/OVERVI EW979-8-3

4、315-4101-9/25/$31.00 2025 IEEE4:25 PM 22.3 A 42Gb/s Singl e-Ended Hybrid-DFE PAM-3 Receiver for GDDR7 Memory I nterfaces Boram Kim,SK hynix,Icheon,Korea In Paper 22.3,SK Hynix presents a 42Gb/s single-ended PAM-3 receiver with a DFE that combines a direct-f eedback and loop-unrolled DFE to minimize

5、area and power overhead f or GDDR7 memory interf aces.4:50 PM 22.4 A 32-to-50Gb/s/pin Singl e-Ended PAM-4 Transmitter with a ZQ-Based FFE and PAM-4 LSB DBI-DC Encoding Yunseong Jo,Hanyang University,Seoul,Korea In Paper 22.4,Hanyang University presents a 32-to-50Gb/s/pin single-ended PAM-4 transmitt

6、er using a ZQ-based FFE and PAM-4 LSB DBI-DC encoding.5:05 PM 22.5 A 0.3pJ/b 32Gb/s/pin Singl e-Ended PAM-4 Receiver with a Del ay-Less Capacitive-Feedback Equal izer Junseob So,Korea University,Seoul,Korea In Paper 22.5,Korea University introduces a 32Gb/s/pin single-ended PAM-4 receiver with a del