XiangShan：符合工业级标准的高性能RISC-V处理器开源项目.pdf

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1、XiangShan:An Open-Source Project for High-Performance RISC-V Processors Meeting Industrial-Grade Standards1 Institute of Computing Technology,Chinese Academy of Sciences2 University of Chinese Academy of Sciences3 Beijing Institute of Open-Source Chip Kaifan Wang1,2,Jian Chen3,Yinan Xu1,2,Zihao Yu1,

2、Zifei Zhang1,2,Guokai Chen1,2,Xuan Hu1,2,Linjuan Zhang1,2,Xi Chen1,2,Wei He3,Dan Tang1,3,Ninghui Sun1,2and Yungang Bao1,2August 20242 2Outline Overview Microarchitecture design Agile development platform Applications in industry&academia Summary3 3Open-Source Chip Ecosystem(OSCE)Empowered by RISC-V

3、Lower the barrier to chip development:reduce time-to-market and costs(IPs,EDA tools,engineers,etc.)Three steps of OSCE:Open ISA Open Design Open ToolsPlatformVerification/SimulationOpen Source Chip EcosystemISAs/IPs/SoCsOS/CompilerCustomized work 90%lines of code4 4 Highest performing open-source pr

4、ocessor series by far Open RTL design with comprehensive documentation Open development tools and platform Address two major challenges in OSCEHosted on GitHub 4.5K stars 630 forksXiangShan:Open-Source High Performance Processors“The Linux of processor”High Performance Expanding computing demand Lac

5、k of high performance open source processors due to design and verification complexityHigh Customizability Industry demand customization and rapid dev iteration Enables domain specific solutions with myriad diverse requirements5 5Two-tier CPU Core Roadmap Designed for high performance Targeting serv

6、er/data-center segment RVA-23 profile Leading RISC-V feature sets(H/V ext.)Kunminghu ArchitectureVersus ARM Neoverse N2 Designed for power/area efficiency Targeting industry-control segment RVA-20 profile Taped out and testedNanhu ArchitectureVersus ARM Cortex A76 Industrial-grade arch design and de