26.d2s4-3-aug23-Exploring Matrix Multiplication Techniques and Enhancements Using RISC-V Custom Extension_Andes_Chris.pdf

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1、Exploring Matrix Multiplication Techniques and Enhancements Using RISC-V Custom ExtensionChun-Nan KeSr.Tech.ManagerAndes TechnologyTaking RISC-VMainstream2Agendal Qualitative Comparison of Matrix Instructionsl Challenges of RVV on Matrix Operationsl SW Scalability/Portability Supportl Efficient Tili

2、ng using VRF Load/Storesl Preliminary Resultsl ConclusionTaking RISC-VMainstream3Qualitative Comparison for Matrix InstructionsProposalPerformancePowerAreaProgram Model FU Utilization-rate Memory Bandwidth Diverse Metrics Context Switch Overhead Data Exchange Efficiency RF Storage R/W port Scalabili

3、ty VLEN AgnosticIntegrated VRF Efficient IO scheme High Utilization-rate High Compute-Mem Ratio Low Dissipation Low YesHybrid Seamless Scalable Outer-Product Support Transpose/Column Access Medium Medium YesAttached Facility Better Physical Implementation Data Compression support Extra Dissipation H

4、igh Yes:Reuse Vector Register:Andes AMM,SiFive Intelligence(not disclosed):Additional Matrix Register:ARM SME:Independent Matrix Register:T-head,Streaming ComputingTodays focusWatchingWatchingTaking RISC-VMainstream4Challenges of RVV on Matrix Operationsl Computational Capacity Challengesn Constrain

5、ed computing power based on vector-product/reduced-suml I/O Efficiency of Tiling VRFn load/store instruction struggles for forming matrix tilesn permute/slide instruction overheads for reshapingl Data Reuse/Localityn Inner product exhibits poor memory bandwidth requirementsl SW Scalabilityn Tiling/w

6、idening present porting difficulties cross diverse VLENsl Boundary/Tail Handlingn Legacy vl csr is inadequate for managing matrix/tensor boundariesTaking RISC-VMainstream5Andes Custom Extension(ACE)on RVVTaking RISC-VMainstream6I/O Efficiency of Tiling VRFl Leverage Standard RVV instructions:n load/