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DCON26_SLIDES_Track14_HolisticDesignOptimizationof3D-ICPackageSubstrateInterconnectionsinMultiplePowerDomai_197_108.pdf

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1、Welcome to ConferenceFebruary 2426,2026Santa Clara Convention CenterExpoFebruary 2526,20261Holistic Design Optimization of 3D-IC Package Substrate Interconnections in Multiple Power Domain Environments based on Hierarchical Reinforcement Learning2Speaker:Seunghun Ryu,(KAIST)Seonghi Lee(KAIST),Dongry

2、ul Park(KAIST),Sanguk Lee(KAIST),Hyunwoo Kim(KAIST),Jinwook Lee(KAIST),Seongho Woo(Keimyung University),Seokbeom Yong(Samsung Electronics),Sangsub Song(Samsung Electronics),Hongseok Kim(CPS Tech,Inc.),Jiseong Kim(KAIST),Seungyoung Ahn(KAIST)SPEAKERS3Seunghun RyuPh.D Student,Korea Advanced Institute

3、of Science and Technology(KAIST)ysh0067kaist.ac.krSeunghun Ryu received the M.S.degree from The Cho Chun Shik Graduate School of Mobility,Korea Advanced Institute of Science and Technology(KAIST),Daejeon,South Korea,in 2022,where he is currently pursuing the Ph.D.degree.In 2022,he was a visiting sch

4、olar at Missouri University of Science and Technology,Rolla,MO.Research interest:High-speed interconnection design,machine learning-based power integrity design optimization for 2.5D/3D ICsContents4I.IntroductionII.Hierarchical Reinforcement Learning FrameworkIII.Analytical Modeling of the Package S

5、ubstrateIV.Verification of Proposed MethodV.ConclusionContents5I.IntroductionII.Hierarchical Reinforcement Learning FrameworkIII.Analytical Modeling of the Package SubstrateIV.Verification of Proposed MethodV.ConclusionMobile APs integrate diverse functions such as CPU,GPU,NPU,modem,and security int

6、o a highly compact footprint,inherently leading to complex challenges in thermal,power,and signal integrity.High Fucntional Density of Mobile AP6DSPVideoEncoder/DecoderCPUMemoryMemoryMemorySLCNPUISP5G ModemMemoryWiFiWGPGPU9.69 mm10.80 mmCPUOS execution,real-time schedulingGPUUI rendering,3D gameISPS

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1. **研究目标**:提出基于分层强化学习(HRL)的3D-IC封装基板优化方法,解决多电源域(MPD)环境下的信号/电源完整性(SI/PI)设计问题。 2. **核心方法**:采用HRL框架,分三层优化(顶层平面布局、中层去耦电容/焊球排列、底层BGA布局),结合单元化建模与节点连接分析,实现高效设计。 3. **性能验证**: - HRL目标函数(𝐹𝑜𝑏𝑗)平均达0.805,优于遗传算法(0.802)和平面强化学习(0.763)。 - 训练时间显著低于传统方法(如GA需46,890秒,HRL推理仅需452秒)。 4. **创新点**:通过单元化模型加速分析(6.3秒 vs. 3D-EM仿真30分钟),并超越基于规则的设计(平均优化提升16.3%)。
3D-IC如何优化? HRL有何优势? 设计如何自动化?
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