DCON26_PAPER_Track01_Adv.SoCICPackagingArchitecture_309_163.pdf

1、1 Advanced SoC/IC Packaging Architecture Dr.Moh Kolbehdari,Socionext USA M Gopalakrishnan Ramakrishnan Socionext USA Gopalakrishnan.R 2 Abstract Monolithic scaling alone no longer delivers the bandwidth-per-watt or memory proximity demanded by AI/HPC and high-I/O platforms.Modern SoC IC package arch

2、itectures from 2.5D interposers to 3D stacks and hybrid bridges now set the envelope for interconnect density,power delivery,thermal paths,reliability,and cost.Recent systems such as NVIDIA GB200/GB300 NVL72 liquid-cooled racks,AMD MI450 Helios platforms,and Intel EMIB/Foveros hybrids exemplify the

3、shift toward rack-scale,package-centric integration.In parallel,wafer-to-wafer(W2W)hybrid bonding is emerging as a disruptive capability,enabling ultrafine-pitch,low-parasitic vertical links and opening new options for memory-on-logic and logic-on-logic stacks.This paper compares five architecture f

4、amilies 2.5D interposers,3D stacks(incl.W2W),3.5D bridges,fan-out RDL,and organic MCM using consistent,testable criteria across:(i)electrical(channel loss/return paths,SI/PI/PDN targets,VRM partitioning),(ii)thermal-mechanical(CTE,warpage,TIM/underfill,hotspot escape),(iii)manufacturability&yield(as

5、sembly windows,rework ability,KGD policies),(iv)test/DFT(diepackageboard access/coverage),and.(v)cost/TTM&sustainability 1-10.Authors Bio Dr.Kolbehdari holds B.Sc.,M.Sc.,and Ph.D.degrees in Electrical Engineering,with doctoral research completed at Temple University(U.S.).He bridges academic rigor a

6、nd industrial execution,developing governed,physics-driven packaging methodologies such as the Tri-Loop(Predict Choose Release)and G G gating framework to deliver predictable yield,reliability,and time-to-market.His current research centers on making packaging architecture auditable,efficient,and sc