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DCON26_PAPER_Track04_MethodstoModelMeasureNoiseMitigationwithEmbeddedCapacitorsinHigh-CurrentPDNsforAICloud_107_16.pdf

上传人: 明**** 编号:1195382 2026-04-16 26页 9MB

1、DesignCon 2026 Methods to Model and Measure Noise Mitigation with Embedded Capacitors in High Current PDNs for AI and Cloud Compute Benjamin Dannan Tyler Huddleston Steve Sandler Heidi Barnes heidi_ Vedashree Chaphekar Kalyan Rapolu Emily Tann Abstract The rapid growth in Data Centers,AI,and superco

2、mputing demands significantly faster edge rates at the package and PCB levels,necessitating superior power delivery network(PDN)solutions.While traditional VRMs and bulk capacitors dominate at lower frequencies,the impact and effectiveness of embedded capacitors in high-current PDNs remain critical

3、for achieving high performance.This paper explores various embedded capacitor technologies and their layout considerations within PCB and package stackups.Through detailed simulation and measurement,we analyze the influence of embedded capacitors on system performance,noise reduction,and power deliv

4、ery efficiency in AI/datacenter applications.We specifically investigate how embedded capacitors impact large signal phenomena,validating findings through both measurements and simulation,and present methods for effectively modeling small signal analysis with these components.We also discuss manufac

5、turing challenges and examine the impact of lateral versus vertical power delivery systems;specifically,we address how vertical power,while more efficient and higher performance due to proximity to the chip,removes the ability to place backside decoupling.This work provides comprehensive insights in

6、to leveraging embedded capacitors to optimize PDN design for next-generation ASICs.Author Biographies Benjamin Dannan,founder and Chief Technologist at Signal Edge Solutions,is a leading expert in signal and power integrity(SI/PI).As a Keysight ADS Certified Expert,he specializes in advanced packagi

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1. **研究背景**:针对AI/云计算高电流PDN需求,传统VRM和电容不足,需嵌入式电容优化性能。 2. **核心发现**:超薄介电材料(如Interra® HK04J)通过**降低回路电感**(12μm材料减少84-90%电感)而非单纯增加电容,显著提升PDN性能。 3. **关键数据**: - 12μm材料外层布局使环路电感降至10-14pH(对比传统89-124pH)。 - 2000A负载下,电压纹波降低17%(4.98V→4.15Vpp)。 - EMI在10-100MHz频段显著抑制。 4. **结论**:超薄材料优化电感是高电流PDN设计关键,未来需结合3oz铜进一步改善热性能。
**电容如何降噪?** **PDN阻抗优化?** **GaN开关优势?**
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