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DCON26_PAPER_Track01_PracticalModelingof3DInterconnectswithHatchedGroundPlanesinSiliconInterposersBridgesFl_140_7.pdf

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1、 Information Classification:General Practical Modeling of 3D Interconnects with Hatched Ground Planes in Silicon Interposer,Bridges,and Flex PCBs HeeSoo LEE,Keysight Technologies hee-soo_,1-707-577-4832 Information Classification:General Seungjoon Yoon,Samsung Electronics ,+82-31-301-7099 Orlando Be

2、ll,GigaTest Labs ,+1-408-594-5279 Jaehyun Cho,WiSOL Co.,Ltd jhchowisol.co.kr Hyeon-Woo Ha,WiSOL Co.,Ltd hwhawisol.co.kr Jinhee Kim,WiSOL Co.,Ltd kimjhwisol.co.kr Taejong Jeong,Keysight Technologies ,+82 2-2004-5293 Tim Wang-Lee,Keysight Technologies tim.wang-,+1 707-577-3255 Information Classificati

3、on:General Abstract The rapid growth of AI/ML market has driven demand for advanced packaging technologies,including silicon interposers and bridges used in chiplets,3DHI,and 3DIC architectures.These structures would require thin layers and gas evacuation during manufacturing,making solid ground pla

4、nes impractical due to the risk of defects like delamination.To address this,patterned ground planes,such as hatched,meshed,or waffles,are used for manufacturability,reliability,and flexibility.Similar issues arise in flex PCBs,commonly found in mobile devices.However,these patterned geometries intr

5、oduce significant modeling challenges for signal and power integrity due to their complexity.Effects include changes in impedance,increased loss,resonance,and crosstalk,all of which require precise modeling to achieve faster design turnaround time and cost reduction.Traditional 2D solvers are often

6、insufficient to deal with higher data rates,and while 3D EM solvers offer accuracy,they struggle with lossy materials and complex stack-ups,especially when 3D interconnects with hatched ground planes are present.This paper introduces a practical modeling approach that uses a specially designed quasi

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1. **背景与挑战**:AI/ML市场驱动先进封装(如硅中介层/桥接器、柔性PCB),需采用镂空地平面(hatched ground planes)解决制造缺陷(如分层),但复杂结构导致信号/电源完整性建模困难。 2. **混合域建模方法**:结合准静态2D场求解器(传输线)与全波FEM求解器(过孔转换区),显著提升效率(如硅桥仿真时间从7.5小时降至<1分钟),同时保持精度。 3. **验证结果**: - 硅桥(UCIe 2.0)与柔性PCB测试案例显示,S参数相似度均值(Mean Similarity Metric)均优于-5 dB(良好匹配),眼图高度差异<2.1%。 - 镂空地平面结构(如矩形/蜂窝状)影响阻抗、损耗和串扰,需优化线宽/间距。 4. **应用价值**:该方法平衡计算效率与精度,适用于高带宽、复杂堆叠的3D互连设计,加速迭代并降低风险。
**如何高效建模?** **hatch地平面有何影响?** **混合建模法如何验证?**
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