DCON26_PAPER_Track02_Scalingto100TbsSwitchesUsingCo-PackagedConnectors_277_9.pdf

1、 Information Classification:General Scaling to 100+Tb/s Switches Using Co-Packaged Connectors(CPC)Authors:Aatreya Chakravarti,Roberto Coccioli,Steven Parker,Lenin Patra,Sina Naderi Shahi,Kapil Shrikhande,Davide Visani Company:Marvell Technologies Information Classification:General Abstract AI/ML wor

2、kloads are rapidly increasing the bandwidth requirements of data-center networks.Next-generation switch ASICs will need to scale to 100 Tb/s,200 Tb/s,and beyond using 512 or 1024 Serdes running at 200Gb/s and 400Gb/s per lane.At these high signaling rates and densities,traditional BGA-based packages

3、 and PCB-routed electrical interfaces are unable to meet the signal-integrity,power,and mechanical demands of systems deployed in cloud and AI data centers.Co-Packaged Connectors(CPC)offer an alternative using direct-to-substrate connectivity that removes BGA transitions,substrate core vias,and PCB

4、routing loss from the channel,improving the SI characteristics of the channel.CPC enables the use of passive twin-ax channels from the switch package directly to the front or back panel connectors of the system,reducing insertion loss(IL)inside the system while increasing link margin for interconnec

5、ts between systems.This paper presents a case for CPC-based switch systems targeting KR-length reaches of 1.5+m cabling at 200 Gb/s,with discussion of loss and reach limits compared with traditional BGA and NPC architectures.Packaging considerations for first-generation 100T CPC packages and scaling

6、 requirements for future 200T-class designs are reviewed,including mechanical integration and attach approaches.Challenges that must be solved to support high radix switch systems and higher baud rates using CPC will be discussed.Information Classification:General Author(s)Biography To be provided.I