DCON26_SLIDES_Track06_FastSignalIntegritySimulationOptimizationforLPDDR5xat10.7GbpsinAIPC_79_127.pdf

1、Welcome to ConferenceFebruary 2426,2026Santa Clara Convention CenterExpoFebruary 2526,20261Fast Signal Integrity Simulation&Optimization for LPDDR5x at 10.7 Gbps in AIPCSpeaker,Feng Ling,(XPEEDIC)Zhijian Mo(Lenovo),Huaqiao Li(Lenovo),Zhengyi Zhu(Lenovo)Mingjie Fang(Lenovo),Guangmeng Ji(XPEEDIC),Yufe

2、ng Dan(XPEEDIC)2SPEAKERS3ImageFeng LingCEO,Xpeedic Technology,IFeng Ling is Founder and CEO of Xpeedic Technology,a leading EDA solution provider for chip-package-system designs.His twenty years industrial career spans from Motorola to EDA startups Neolinear(acquired by Cadence)and Physware(acquired

3、 by Mentor Graphics).In 2009,he founded Xpeedic Technology,continuing the efforts to bring the novel EDA solutions to the semiconductor industry.Dr.Ling received his Ph.D.degree in electrical engineering from the University of Illinois at Urbana-Champaign(UIUC)in 2000.4Outline Background Fast Signal

4、 Integrity Simulation of LPDDR5X Channels:Detailed Process OverviewDOE-Based Simulation MethodDOE Simulation FlowDOE-Based Optimization of LPDDR5X Channels PCB Design Optimization:Stack-up optimizationRouting layer optimization CCT-Based Optimization:CCT TheoryCCT Simulation FlowCCT-Based Channel Ev

5、aluation System validation result SummaryBackground 5Figure1 Memory bandwidth requirements of LLM workloadsFigure2 Trace width and trace spacingFigure3 Routing layer,via stub,and spacing between DRAM and CPUFast Signal Integrity Simulation of LPDDR5X Channels6When operating at 10.7 Gbps,LPDDR5X sign

6、als face severe signal integrity challenges:First,the very fast signal edge transitions introduce significant high-frequency spectral content,increasing sensitivity to loss and discontinuities.Second,the operating voltage swing is very small,with supply voltages around 1.05 V or lower,resulting in a