DCON26_SLIDES_Track07_BreakingBarriersin448GbpsSerialLinksBandwidthESDLinearityChallengesinHigh-OrderPAMSys_137_149.pdf

1、Welcome to ConferenceFebruary 2426,2026Santa Clara Convention CenterExpoFebruary 2526,2026 1Breaking Barriers in 448 Gbps Serial Links:Bandwidth,ESD,and LinearityChallenges in High-Order PAM SystemsPrabhnoor Kainth(Neuron IP)Jhoan Salinas(Neuron IP),Richard Lin(Neuron IP)Saman Sadr(Neuron IP)2ImageS

2、PEAKERSPrabhnoor KainthSignal Integrity&Analog Design Engineer,Neuron IPPrabhnoor is a Signal Integrity&Analog Design Engineer at Neuron IP,specializing in the analysis of high-speed circuits and mixed-signal system-level validation for SerDes&D2D IP.He previously worked at Rambus&Semtech,focusing o

3、n advanced packaging design,silicon interface IPs,and electrical characterization.Prabhnoor received his BASc and MEng in Electrical Engineering from the University of Toronto.3Motivation:Why 400G?4AIs Insatiable Hunger The Driver:Exponential growth of AI workloads is placing unprecedented demands o

4、n datacenter interconnects The Scale:Training clusters now span tens of thousands of accelerators,requiring terabytes per second of bandwidth The Bottleneck:Current 112 Gbps and 224 Gbps interfaces are insufficient to sustain next-gen GPU/TPU scaling The Goal:We must transition to 448 Gbps per lane

5、to keep pace with the 4-5x annual compute growth 1-3The 448 Gbps Challenge5 Bandwidth Wall:Scaling PAM4 to 448 Gbps requires 224 Gbaud Nyquist Limitation:This pushes the Nyquist frequency to 112 GHz,which is well beyond the practical range of most analog components The Alternative:Higher-order modul

6、ation(PAM6,PAM8)is necessary to reduce the baud rate and Nyquist frequency requirements 4PAM6PAM8Trade-offs in High-Order Modulation6Frequency Relief:PAM6 Nyquist 87 GHzPAM8 Nyquist 75 GHzNew Constraints:Linearity:More eye levels reduce voltage swing per eye,making the system highly susceptible to s