DCON26_SLIDES_Track01_Adv.SoCICPackagingArchitecture_309_90.pdf

1、Welcome to ConferenceFebruary 2426,2026Santa Clara Convention CenterExpoFebruary 2526,20261Advanced SoC/IC Packaging ArchitectureMoh Kolbehdari(Socionext),Rama Gopalakrishnan(Socionext)What this is From physics modeling to qualified ramp PDN/VRM,SI/PI,thermal/mechanical,CTE,warpage,materials,yield,a

2、nd reliability under one governed framework ScopeAdvanced SoC package integration:power delivery,signal integrity,thermal/mechanical stress,materials/assembly,yield,reliability.ObjectiveShow a manufacturable path from concept(G0)to qualified ramp(G5)with enforceable gates and stop conditions.ClaimTh

3、is is an execution framework in active use.We deliver a customer-ready stack,not a slide concept.Innovative solutions for Advanced SoC/IC Packaging2“One Dashboard.One Gate.One Truth.”3Executive Abstract Proposal:Present a unified framework that governs Predict Choose Release(P/C/R)phases across desi

4、gn,manufacturing,and reliability for advanced SoC and 2.5D/3D/3.5D integration.Innovation:Introduces the Tri-Loop Co-Architecture linking CPM PDN/VRM CTM to co-optimize electrical,thermal,and mechanical domains under quantitative gates(G0G5).Execution Model:Embeds DOE surrogate Monte Carlo Pareto op

5、timization inside governed gates,ensuring that every design iteration carries measurable risk ownership.Cross-Loop Unification:Merges electrical-thermal-mechanical sign-off into a single governed dashboard;each gate requires correlated evidence,not assumption.Key Deliverables:Correlated PDN Bode/Z_t

6、arget,SI/PI margin,CTM T_tile,warpage envelope,yield and reliability readiness;all verified on EVT hardware.Results/Impact:Converts packaging execution from“best effort”to provable readiness,enabling high-current(1 kA)AI/HPC SoCs to meet low-cost,yield,lifetime,and time-to-market concurrently.Pillar