DCON26_SLIDES_Track02_ModelingStudyofPowerSupplyNoisePSNinServerDDRLinks_184_96.pdf

1、Welcome to ConferenceFebruary 2426,2026Santa Clara Convention CenterExpoFebruary 2526,2026 1Modeling&Study of Power Supply Noise(PSN)in Server DDR LinksKanupriya Bhardwaj,(AMD)Kanupriya Bhardwaj(AMD),Ehsan Tabasy(AMD),Jeremy Walker(AMD),Chai Palusa(AMD)2SPEAKERKanupriya BhardwajSenior Member of Tech

2、nical Staff,AMDKKanupriya Bhardwaj received the B.Tech.and M.Tech.degrees in Electrical Engineering from IIT Kharagpur,India,in 2007,and Ph.D.from Stanford University in 2013.She has since worked at Intel and Altera and is currently at AMD,working on performance modeling of links.3 Motivation DDR Si

3、gnals and Sources of Power Supply Noise(PSN)PSN Impact on Voltage Margins Power Delivery Network(PDN)analysis Modeling of Transient PSN profile using Hybrid Methodology Characterizing Link Performance Application to LTI based Tools ConclusionOUTLINE4 Server DDR entails multiple parallel,area-optimiz

4、ed lanes DDR5 and DDR6 are more sensitive to voltage noise Lower operating voltagesOn-DIMM PMICs introducing new noise sources Increased data rates and tighter timing windows Power supply noise(PSN)important for link budgetingMOTIVATION5 Swing is entirely dependent on the DB/DRAM supply Ron/Rtt rati

5、o determines the swing and reflections For Ron=Rtt,Vdd=1V Swing=0.5V Common Mode Voltage(VCM)of 0.75V DDR SIGNAL VOLTAGE PROFILE6=+=+2 +Realistic scenario where each power supply source carries noise Since signaling is single ended,the Rx AFE generates a reference voltage,which carries a part of the

6、 PSN Assuming that the terminations are equal,(i.e.,Ron=Rtt).WRITE :Rtt(Vdd referred)on the Data Buffer/DB READ :Rtt(Vdd referred)on the Host/CPUDDR PSN SOURCES on HOST and DRAM/DB 7 Output High(VOH)and Output low(VOL)voltages For READ mode For WRITE mode PSN Voltage Impact on Margins 8Impact of PSN