当前位置:首页 > 报告详情

DCON26_PAPER_Track01_SuperchargingSoCPowerIntegritywithSiliconCapacitors_47_8.pdf

上传人: 明**** 编号:1195409 2026-04-16 16页 1.50MB

1、 Information Classification:General Supercharging SoC Power Integrity with Silicon Capacitors Luca Vassalli,Empower Semiconductor L Mukund Krishna,Empower Semiconductor M Information Classification:General Abstract The rise of AI and high-performance computing(HPC)is pushing the limits of power deli

2、very design.As xPUs grow in complexity,power density,and I/O bandwidth,maintaining power integrity across System on Chip(SoC)platforms becomes increasingly difficult.Traditional power delivery networks(PDNs),which rely heavily on ceramic decoupling capacitors are now reaching fundamental limitations

3、.Chief among these is parasitic inductance which leads to impedance peaking at mid-frequencies and degrades overall system performance.This paper introduces silicon capacitors as a breakthrough solution to these power integrity challenges.Offering almost ideal ESL,ultra-thin profiles,and flexible in

4、tegration into package substrates,silicon capacitors significantly flatten PDN impedance and suppress mid-frequency noise that conventional approaches fail to address.These devices enable proximity decoupling directly at the point of load,improving transient response and unlocking performance in den

5、se chiplet-based architectures.System-level PDN models,impedance vs.frequency comparisons,and cross-sectional package diagrams will be presented,to illustrate capacitor placement strategies.Application-specific examples including real product imagery will demonstrate the practical applications and b

6、enefits of silicon capacitors in designs.The configurability of silicon capacitors in terms of thickness,termination types,and form factors will also be discussed to support implementation across varied packaging platforms.Author(s)Biography Luca Vassalli is the Director of customer applications eng

word格式文档无特别注明外均可编辑修改,预览文件经过压缩,下载原文更清晰!
三个皮匠报告文库所有资源均是客户上传分享,仅供网友学习交流,未经上传用户书面授权,请勿作商用。
1. **背景与挑战**:AI/HPC推动SoC功率密度提升,传统MLCC因高ESL(约200pH)导致PDN中频阻抗峰值,影响性能。 2. **硅电容解决方案**:硅电容(如EC1004)ESL低至20pH,体积密度达30μF/mm³(MLCC仅2.2μF/mm³),可嵌入封装(如substrate core或landside),显著抑制中频噪声(阻抗降低2倍以上)。 3. **性能优势**: - 稳定性:高低温/电压下电容稳定(图2); - 功耗降低:50mV电压纹波减少可节省13%功耗(如750mV供电); - 设计灵活性:支持多终端、定制厚度(50-750μm)及封装形式(图4、9)。 4. **应用效果**:嵌入硅电容后,PDN阻抗在100MHz以上频段降低3-8倍(图7、8),支持更高TDC或更低工作电压,提升能效。
**硅电容优势?** **PDN如何优化?** **高频噪声如何抑制?**
客服
商务合作
小程序
服务号
折叠