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DC25_PAPER_Track10_DeterminingTheRequirementsDievsPackage_Phillips.pdf

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1、 Determining the Requirements,Die vs.Package vs.Board:Multi-level Power Distribution Network Design John Phillips,Cadence Shirin Farrahi,Cadence Kristoffer Skytte,Cadence Ethan Koether,Amazon Joseph Hartman,Oracle Mario Rotigni,retired mario.rotigniieee.org Istvan Novak,Samtec P a g e 2|27 Abstract

2、System design engineers face increasingly difficult power distribution network(PDN)design targets,with varying design and hardware delivery dates for chips,packages,and PCBs.Ensuring a functional PDN under these conditions is challenging.This paper explores PDN requirements at the chip,package,and P

3、CB levels,offering guidelines to understand tradeoffs and solutions.The paper introduces an updated target impedance methodology that varies with frequency and spatial position for shared PDNs.Two power delivery strategies are examined:single point-of-load PDNs and PDNs feeding multiple parallel loa

4、ds.The required bandwidth(BW)of the PDN response depends on the supply network location.The paper aims to correlate BW changes with major PDN components from the DC source to silicon.It highlights that impedance requirements differ across the system due to spatial filtering effects.Power integrity e

5、xperts must decide whether to combine power rails or provide separate power for each device.Using a high-power processor-based server system,the paper measures and simulates power rail impedance at various PDN points.The findings offer guidelines to avoid over-designing PDNs and to understand consid

6、erations for complex multi-load power deliveries.Authors Biography Ethan Koether is a Senior Signal Integrity and Power Integrity Engineer with Amazon Project Kuiper.Prior to this,he spent seven years at Oracle as a hardware engineer in the volume server space.Ethan earned his BS in Electrical Engin

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1. **PDN设计挑战**:芯片、封装、PCB多级电源分配网络(PDN)设计面临阻抗目标随频率和空间位置变化的挑战,需权衡单点负载(POL)与多负载并行供电策略。 2. **空间滤波效应**:PDN存在天然低通滤波(如封装-芯片谐振衰减高频噪声),阻抗要求随位置变化(如芯片需低阻抗,电源端可放宽)。 3. **实测与仿真验证**:通过两个高功率服务器案例(POL配置DUT1和多负载DUT2),测量阻抗低至μΩ级,证实空间滤波导致阻抗差异(如DUT1自阻抗vs转移阻抗)。 4. **关键数据**:DUT1 DC电阻920-990μΩ/引脚,DUT2空间滤波截止频率10kHz-1MHz(10dB/ decade衰减),MLCC谐振频率(如8MHz)显著影响阻抗平坦度。 5. **设计指导**:避免过度设计,利用空间滤波简化多负载PDN,需结合实测与仿真优化。
**PDN设计挑战** **阻抗优化策略** **多负载供电方案**
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