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DC25_PAPER_Track01_FastDesignAndSimulation_Dai.pdf

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1、 Fast Design and Simulation of Photonics Computing Chip Base on Chiplet-based Heterogeneous Integration Wenliang Dai,Xpeedic Co.,LTD Mingyang Jiang,Lightstandard(Suzhou)Co.,LTD.jiangmingyanglightstandard.co Xuanjiang Shen,Lightstandard(Suzhou)Co.,LTD.shenxuanjianglightstandard.co Abstract Photonic c

2、omputing technology based on large-scale matrices has been shown to surpass Moores Low and meet the increasing demand for high computing power,energy efficiency,and the ability to solve complex tasks.However,photonic computing also presents significant challenges in package design and simulation due

3、 to its complex heterogeneous integration of silicon photonic chips and electronic components.In this paper,we propose a rapid design and simulation method for photonic computing chips based on the heterogeneous integration of chiplets.Various digital-to-analog(DAC)chips for electro-optic modulators

4、(EOM)and weights,as well as analog-to-digital converter(ADC)chips for photodetectors(PD)and photonic computing chips on silicon interposers,offer enhanced higher bandwidth and reduced latency,while accommodating a large number of input/output(I/O)connections and micron-scale structures.To sustain su

5、ch high density and bandwidth,we investigate and compare several routing strategies using a new fast signal integrity analysis method,which includes both pre-sim and post-sim evaluations.Additionally,we optimize mesh ground parameters,which involve constructing accurate channel models through templa

6、tes and GDS files,and performing rapid analyses in both frequency and time domains using the Input/Output Buffer Information Specification(IBIS)model.This comprehensive approach ultimately enables automatic full signal coverage.Author(s)Biography Wenliang Dai,Co-Founder,VP of Xpeedic.Received the M.

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1. **技术背景**:光子计算芯片基于硅中介子(Si interposer)的2.5D异构集成,通过chiplet技术实现硅光子芯片与电子芯片(如DAC/ADC)的高密度互连,提升带宽并降低延迟。 2. **设计挑战**:多芯片布局、I/O凸点阵列规划、高密度自动布线(如10,000+模拟权重信号布线),以及信号完整性(SI)和电源完整性(PI)优化。 3. **核心方法**: - 采用3D IC Compiler实现自动化布线,结合MoM电磁仿真器进行预/后SI仿真。 - 预仿真优化布线参数(如线宽/间距),Pattern1(GSGS结构)在1GHz下插入损耗(IL)-3.29dB,远端串扰(FEXT)-38.79dB。 - 后仿真通过IBIS模型完成12.5Gbps SerDes信号眼图分析,电压余量充足。 4. **PI优化**:12个电源域的DC IR-Drop仿真显示最大压降8.3mV(0.9V/230mA),满足设计目标。 5. **成果**:实现光子计算芯片2.5D封装的快速设计与验证,支持高带宽、低延迟计算需求。
光电芯片设计难点? 2.5D集成如何优化? 信号完整性如何保障?
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