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DC25_SLIDES_TRACK13_FreeSignalIntegrityHowUnderstanding _Skytte_FINAL.pdf

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1、Information Classification:GeneralWelcome to ConferenceJanuary 2830,2025Santa Clara Convention Center1ExpoJanuary 2930,2025Information Classification:GeneralFree signal integrity?How understanding anisotropic materials and tolerances could increaseperformance at 112/224Gbps and beyondEric Bogatin(Un

2、iversity of Colorado)Kristoffer Skytte(Cadence)Alfred P.Neves(Wild River Technology),John Phillips,(Cadence),Frank Zavosh(Cadence)2Information Classification:GeneralSPEAKERS3Eric BogatinProfessor,University of Coloradoeric.bogatincolorado.eduEric Bogatin is a Professor at the University of Colorado,

3、Boulder where he teaches undergraduate and graduate courses on signal integrity and system design.Additionally,he is the Dean of the Teledyne LeCroy Signal Integrity Academy,at www.beTheS and a Fellow with Teledyne LeCroy.He is also the technical editor of the Signal Integrity JournalKristoffer Skyt

4、teApplication Engineer Architect,CKristoffer Skytte has 20 years experience working on chip,package,board and full system analysis including SI,PI,thermal,and EMC challenges.His recent efforts are on examining differences between measurement and simulation.He holds an M.Sc.EE.degree from the Technic

5、al University of Denmark.ImageInformation Classification:GeneralJohn PhillipsSr.Principal Application Engineer,CJohn has 30+years experience working on SI,PI,and EMC challenges at the chip,board,and system level in applications including high-end computing and mil-aero.He holds an MSc.from Bolton Un

6、iversity,UK.His current interests are SI/PI co-simulation and modelling for high-speed interfaces.Image SPEAKERSAlfred P.NevesFounder and Chief Technology Officer at Wild River TAl has 39 years of experience in the design and application development of semiconductor products,capital equipment design

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1. **会议主题**:2025年1月28-30日圣克拉拉会议中心,探讨112/224Gbps及以上信号完整性,聚焦材料各向异性和公差影响。 2. **核心问题**:设计(AD)与制造(AF)硬件差异导致插入损耗(IL)余量不足,表面粗糙度是主要误差源(Hausdorff指标63.3)。 3. **各向异性影响**:PCB介电常数各向异性(Λ=5-20%)使过孔阻抗变化达7%(如20%各向异性时Z_via降6.1%),而微strip仅降0.5%。 4. **材料识别**:AI优化后,预浸料Dk较设计值高10%(3.11→3.29),表面粗糙度从0.069μm增至0.148μm。 5. **制造公差**:线宽±0.5mil或介质厚度±10%显著影响阻抗(如Beatty线阻抗波动达±7.2%)。 6. **结论**:需通过数字孪生模型校准IL余量,并分离各向异性与制造公差的影响。
信号完整性如何提升? 各向异性有何影响? 设计与制造差异多大?
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