DC25_SLIDES_Track5_OffChipDesignMethodFor_Park.pdf

1、Information Classification:GeneralWelcome to ConferenceJanuary 2830,2025Santa Clara Convention Center1ExpoJanuary 2930,2025Information Classification:GeneralOff-Chip Design Method for Improving Signal Integrity in Multi Branch Parallel interface of Non-Volatile MemoryJiwoon Park(Samsung Electronics)

2、Sujin Kim1,Soyoung Jung1,Kwangsoo Park1,Jihyung Jung1Juhwan Lim1,Jaesang Yun1,Youngmin Ku1,Sunghoon Chun11 Samsung Electronics2Information Classification:GeneralImageSPEAKERSJiwoon ParkPrincipal Engineer,Samsung EJiwoon Park received the B.S degree in information and communication engineering from I

3、nha University,Incheon,South Korea,in 2006 and the M.S degree in electrical engineering from the Korea Advanced Institute of Science and Technology(KAIST),Daejeon,South Korea,in 2008.In 2008,he joined Samsung Electronics,Hwaseong,South Korea,and is currently a principal engineer for improving off-ch

4、ip SI/PI of Solid State Drives(SSD).He has 20 US patents in related to signal Integrity for parallel interface.His current research interests include overcoming interface speed limit for off-chip channel of high capacity SSD with toggle 6.0,LPDDR5 interfaces.3Information Classification:GeneralOUTLIN

5、E4IntroductionCase Study and Analysis of Multi Branch InterfaceReflection Analysis&Crosstalk AnalysisPower NoiseOptimal VOH level for LTT/PI-LTTNovel Off-Chip Design Methods for Multi Branch InterfaceReflection-Controlled Branch(RCB)MethodPractical Channel Optimization Method using Reinforcement Lea

6、rningVerification of RCB Method in Multi Branch TopologyConclusionInformation Classification:GeneralArchitecture of Solid State Drive(SSD)5ControllerBufferFlashPackage 0 Channel 0FlashPackage 1 FlashPackage 0 Channel 1FlashPackage 1 DDR,LP Toggle,OnFiPCIeDriverODTCTT(Center-Tapped Termination)Driver