DC25_SLIDES_Track12_MethodologyAccuratePCIeReceiverTesting_Stangel_V3.pdf

1、Information Classification:GeneralWelcome to ConferenceJanuary 2830,2025Santa Clara Convention Center1ExpoJanuary 2930,2025 Information Classification:GeneralMethodology for Accurate Receiver Testing in PCIe using Measured Step Response based Stressed Eye CalibrationKarsten Stangel(Intel Corporation

2、)Dean Gonzales,Ethan Crain,Gurpreet Narula,Abdul Rehman(AMD)Ricardo Baca,Christiaan Bil,Patrick Kennedy,Manjari Kulkarni,Manisha Nilange,Mohiuddin Mazumder,Kyle Sheahan(Intel Corporation)2Information Classification:GeneralImageSPEAKERSKarsten StangelAnalog Platform Architect,Intel CKarsten is an ana

3、log platform architect at Intels Data Center&AI group.He received his diploma in electrical engineering from the University of Duisburg,Germany,in 1999.His current focus covers pathfinding and feasibility of next generation High-Speed IO technologies,development of standards,specifications,and valid

4、ation methodologies.3Information Classification:General High level Overview of PCIe Receiver Jitter Tolerance Validation Measured Step Response based Rx Stressed Eye Calibration Methodology Calibration Channel Reflections of various Topologies and their impact on Stressed Eye Analysis of measured St

5、ep Response Quality and possible Improvements Instrument to Instrument Variability of Step Response Quality and Averaging Conclusion and SummaryAgenda4Information Classification:General Jitter tolerance test is the corner stone validation item in PCIeto ensure Rx specification compliance and robustn

6、ess BERT sends and receives compliance pattern to DUT Calibration channel with maximum loss as per spec(e.g.PCIe 6.0 32dB)Impairments are applied to provide a stressed eye to DUT RxPCIe Receiver Jitter Tolerance(Jtol)Validation5 Jitter Tolerance Mask with pass/fail regionJtol curve describes Receive