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DC25_SLIDES_Track6_DirectToSubstrateCPC_Krooswyk.pdf

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1、Information Classification:GeneralWelcome to ConferenceJanuary 2830,2025Santa Clara Convention Center1ExpoJanuary 2930,2025 Information Classification:GeneralDirect to Substrate 200G-PAM4 Co-Packaged Connectors:Is it a Reality?Steve Krooswyk,SamtecJignesh Shah(Samtec),Evan Beauprez(Broadcom)Regee Pe

2、taja(Broadcom)2Information Classification:GeneralImageSPEAKERSSteve KrooswykSr SI Design,Samtecsteve.krooswyk samtecSteve is technical lead in Samtecs high speed connector and cable development group.His 20 years of experience includes a role as PCI Express lead in Intels Data Center Group,introduci

3、ng excursion metrics in the PCI-SIG,co-authoring High Speed Digital Design for High Speed Interconnects&Signaling,and an MS from U.of South Carolina.3Information Classification:GeneralSystem challenges are amplified more than ever Doubling of data rate Density Thermal Signal IntegrityWe desire to in

4、crease the#of I/O at the front and back of the chassis Data Center Connectivity 4Information Classification:GeneralAchieving the I/O needs through PCB routing is suffering a challenge:Long lengths to the front andor back mean higher losses Ultra-low loss material is 2x the loss from 26 to 53 GHz Agg

5、ressive surface roughness is required to further managethe losses Package core,solder ball,and escape via add reflection&crosstalk cannot be tolerated at longer lengths(worse SNR)On Board Limitations52.8dbinch1.4dbinchInformation Classification:General Co-Packaged connectivity presents an opportunit

6、y to reduce package vertical SI penalties The lower loss of cables and removal of package-related reflections allow an extended reach Channel models assembled below reveal the value add Solutions reached through loss budget trade off and preliminary COM simulation Channel Modeling w Copper DAC Cable

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1. **会议信息**:2025年1月28-30日于圣克拉拉会议中心举办,主题为“200G-PAM4直接基板印刷与共封装连接器现实性”。 2. **核心挑战**:数据中心I/O需求增长,PCB布线面临高损耗(如2.8dB/英寸)、信号完整性问题及封装反射/串扰。 3. **CPC方案优势**: - 1米链路损耗降至22dB(53GHz),误码率<1e-13; - 高密度设计(1024 DP,100×100mm封装),针脚间距0.4-0.5mm; - 低串扰(屏蔽设计)及可分离接口(控制stub长度±0.3mm)。 4. **关键技术**:焊接附件可靠性验证,阻抗控制(92.5Ω),112G OSFP连接器兼容。 5. **结论**:CPC通过减少封装损耗和反射,实现长距离、高密度连接,满足224G系统需求。
**CPC技术优势?** **高密度连接挑战?** **如何实现低损耗?**
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