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DC25_SLIDES_Track10_DeterminingTheRequirementsDievsPackage_Phillips_v02.pdf

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1、Information Classification:GeneralWelcome to ConferenceJanuary 2830,2025Santa Clara Convention Center1ExpoJanuary 2930,2025 Information Classification:GeneralDetermining the Requirements,Die vs.Package vs.Board:Multi-level Power Distribution Network DesignEthan Koether(Amazon)John Phillips,(Cadence)

2、,Shirin Farrahi(Cadence),Kristoffer Skytte(Cadence),Joseph Hartman(Oracle),Mario Rotigni(Retired),Istvan Novak(Samtec)2Information Classification:GeneralImageSPEAKERSEthan KoetherSr.Signal and Power Integrity Engineer,Amazon Project KuiperKEthan Koether earned his masters degree in EECS in 2014 from

3、 MIT then spent seven years as a hardware engineer at Oracle.He then joined Amazons Project Kuiper as a Sr.SIPI engineer.His interests are in commercial power solutions and power distribution network design,measurement,and analysis.3Information Classification:GeneralImageImage SPEAKERSKristoffer Sky

4、tteApplication Engineer Architect,CKristoffer Skytte has 20 years experience working on chip,package,board and full system analysis including SI,PI,thermal,and EMC challenges.His recent efforts are on examining differences between measurement and simulation.He holds an M.Sc.EE.degree from the Techni

5、cal University of Denmark.Shirin FarrahiSr.Principal Software Engineer,CShirin Farrahi is working on SI and PI tools for automated PCB design.Prior to joining Cadence,she spent four years as a Hardware Engineer in the SPARC Microelectronics group at Oracle.She received her Ph.D.in Electrical Enginee

6、ring from the Massachusetts Institute of Technology.4ImageImage John PhillipsSr.Principal Application Engineer,CJohn has 30+years experience working on SI,PI,and EMC challenges at the chip,board,and system level in applications including high-end computing and mil-aero.He holds an MSc.from Bolton Un

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1. **会议与主题**:2025年1月28-30日圣克拉拉会议中心,主题为多级电源分配网络(PDN)设计,探讨芯片、封装与板级设计差异。 2. **核心目标**:更新目标阻抗方法(频率与空间位置函数),对比POL(负载点)与并行负载PDN差异,关联带宽变化与PDN组件,避免过度设计。 3. **关键数据**: - DUT1(AI应用):BGA阻抗<1mΩ(10kHz-3MHz),净电感<0.25nH。 - DUT2(高计算应用):32 DIMM插座,4个80A电源平面,阻抗最低至10μΩ(MLCC谐振频率)。 4. **测量与仿真**:VNA实现10μΩ噪声 floor(优化后1μΩ),仿真与测量在高频存在偏差(如8MHz未建模的封装去耦)。 5. **结论**:目标阻抗需适配应用,PDN低频RC滤波(~10kHz)及高频MLCC谐振是关键。
**PDN设计新法?** **阻抗如何优化?** **噪声如何抑制?**
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