DC25_SLIDES_Track5_PSIJBasedIntegratedPowerIntegrity_Shin.pdf

1、Information Classification:GeneralWelcome to ConferenceJanuary 2830,2025Santa Clara Convention Center1ExpoJanuary 2930,2025Information Classification:GeneralPSIJ Based Integrated Power Integrity Design for HBM Using Reinforcement Learning:Beyond the Target ImpedanceSpeaker:Taein Shin(KAIST)Paper Aut

2、hors:Taein Shin(KAIST),Hyunwook Park(Missouri S&T),Boogyo Sim(KAIST),Keunwoo Kim(KAIST),Keeyoung Son(KAIST),Joonsang Park(KAIST),Haeyeon Kim(KAIST),Hyunjun An(KAIST),Jiwon Yoon(KAIST),Joungho Kim(KAIST)2Information Classification:GeneralImageSPEAKERTaein ShinPostdoctoral Researcher,Korea Advanced In

3、stitute of Science and Technology(KAIST)taeinshinkaist.ac.kr/https:/ in 2.5D/3D high performance systems-SI/PI design using machine Learning(Reinforcement Learning)-SI/PI in high bandwidth memory(HBM)package3Co-authors Hyunwook Park(Missouri S&T)Boogyo Sim(KAIST)Keunwoo Kim(KAIST)Keeyoung Son(KAIST)

4、Joonsang Park(KAIST)Haeyeon Rachel Kim(KAIST)Hyunjun An(KAIST)Jiwon Yoon(KAIST)Prof.Joungho Kim(KAIST)Information Classification:General Introduction Proposal of PSIJ based HBM I/O Interface Optimization Method using RL Modeling of System-Level PSIJ in HBM I/O Interface for Reward Estimator Verifica

5、tion of the Proposed Method Analysis of Design Results with Jitter Tracking Summary and ConclusionContents4Information Classification:GeneralIncreased Power Supply Noise Induced Jitter(PSIJ)Proportion of Total Jitter5Huge transient current(1024 I/Os)No scaling down of package technologyGPU1024 I/O C

6、hannelsPHYHBMHostPCB/PackageSilicon InterposerPHYP/G planePSIJ Compact size and power efficiencyHigher speed I/O operationlonger clock path problem2134Information Classification:GeneralNecessity of Reinforcement Learning Framework for System-Level I/O Interface Design with PSIJ6Power Distribution Ne