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DC25_SLIDES_Track13_CascadedPackageToPCBChannel_Peng.pdf

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1、Information Classification:GeneralWelcome to ConferenceJanuary 2830,2025Santa Clara Convention Center1ExpoJanuary 2930,2025Information Classification:GeneralCascaded Package to PCB Channel Simulation Method Considering Different High-speed 3D Interconnect Models Extended to Higher Bandwidth up to 75

2、 GHz Zhekun Peng,Missouri University of Science and TechnologyChaofeng Li,Missouri University of Science and TechnologyJunyong Park,Missouri University of Science and TechnologySathvika Bandi,Missouri University of Science and TechnologySantosh Pappu,Meta PlatformGranthana Rangaswamy,Meta PlatformXu

3、 Wang,Meta PlatformSrinivas Venkataraman,Meta PlatformDongHyun(Bill)Kim,Missouri University of Science and Technology2Information Classification:GeneralSPEAKERSZhekun PengPh.D.in Missouri University of Science and Technology,EMC lab pengzhemst.eduZhekun Peng received the B.S.degree in electronic and

4、 information engineering fromHuazhong University of Science and Technology,Wuhan,China in 2019.He is currentlyworking toward the Ph.D.degree in electrical engineering at EMC Laboratory,MissouriUniversity of Science and Technology.His research interests include corona discharge on glass,on-chip ESD,S

5、erDes high-speed channel analysis,through-silicon via technology and EMI measurement.He worked as an EMC Design Engineering Intern at Apple Inc.in 2023.Mr.Peng wasthe recipient of DesignCon 2021 Early Career Best Paper Award and 2024 IEEE JointEMC Japan/APEMC Risaburo Sato Award(Best Paper Award).Mr

6、.Peng was therecipient of 2024 EMC Society Presidents Memorial Award.3Information Classification:GeneralIntroduction Package-PCB Channel Simulation4Complexity of simulating end-to-end package and PCB channel performance.Long 3D finite element method(FEM)simulation time.Complexity of simulation:Large

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1. **研究目标**:提出级联方法简化高速通道(75GHz+)仿真,解决全通道3D仿真复杂度高、耗时长问题。 2. **核心方法**: - **互连(Inter-connection)**:采用半焊球切割(Half-solder ball cutting),确保波连续性,S参数与TDR结果在85GHz内匹配良好。 - ** intra-connection**:通过3D模型切割+2D分析替代中间层,内存需求从388GB降至60MB,仿真时间从75h缩短至6min。 3. **应用优势**:支持快速评估不同长度通道(单位插入损耗0.16–0.193dB/mm)、串扰故障排查(如定位焊球附近屏蔽不足),并验证了CPC(共封装铜)案例的可行性。 4. **创新点**:首次将级联方法扩展至75GHz以上,兼顾精度与效率,适用于224G PAM4等高速设计。
**如何提升仿真效率?** **高速通道如何优化?** **焊接球如何减少失配?**
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