DC25_SLIDES_TR10_BalancingCurrentDensityToHigh_Hostetler.pdf

1、Information Classification:GeneralWelcome to ConferenceJanuary 2830,2025Santa Clara Convention Center1ExpoJanuary 2930,2025 Information Classification:GeneralBalancing Current Density to High-Power ASICs in Lateral Power Delivery DesignsBrian Hostetler,Hewlett Packard Enterprise2Information Classifi

2、cation:GeneralImageSPEAKERBrian HostetlerPower Integrity Engineer,Hewlett Packard EBrian is a senior electrical engineer at HPE,specializing in power integrity.He is responsible for the design of power delivery networks for Cray supercomputer systems.He develops cabinet-level and board-level designs

3、,simulations,and measurements.He is also responsible for the design and verification of ultra-low jitter clock solutions for next-generation ASICs.He holds degrees from Indiana State University and Purdue University.3Information Classification:GeneralMOTIVATION4ASIC/CPU/GPU power is increasing1 amp

4、per ball is no longer feasibleLimit maximum PCB via currentAvoid thermal via failuresPromote even current density through packageMinimize lateral package current and power lossAvoid electromigration at die bumpsInformation Classification:GeneralAPPLICATION5ASIC ball mapPCB layoutInformation Classifi

5、cation:GeneralBALANCING CONCEPT6Information Classification:GeneralPOWER PLANE VOLTAGE DROP7 4 mV gradient on layer 18(VDD)Initial simulation(no modifications):Need approximately 4 mV/2 A=2 m extra via resistance785mV780mVInformation Classification:GeneralTYPICAL VIA RESISTANCE81.7 m difference betwe

6、en 7.9 mil and 24 mil viasInformation Classification:GeneralWEBBING IMPACT9Information Classification:GeneralINITIAL SIM(NO MODIFICATIONS)10Layer 18 Current Density 50 A/mm2 in perimeter webbing 10 A/mm2 in central webbing92 A/mm20 A/mm2Information Classificat