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DC25_SLIDES_Track12_PracticalImplementationOfInsertionLoss_Diminico_V3.pdf

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1、Welcome to ConferenceJanuary 2830,2025Santa Clara Convention Center1ExpoJanuary 2930,2025 Practical implementation of insertion loss correction and delay characterization of test fixtures used for 200 Gb/s per lane conformance2Speaker:Christopher DiMinico;MC Communications/PHY-SI/SenTekseSpeaker:Ale

2、ssio Alaimo,Cisco SystemsSpeaker:Jason Ellison,TE ConnectivityAuthors:Christopher DiMinico,MC Communications/PHY-SI,LLC/SenTekse LLC,Alessio Alaimo,Cisco Systems,Jason Ellison,TE Connectivity,Mike Resso,Keysight,O.J.Danzy,KeysightRick Rabinovich,Keysight,Richard Mellitz,Samtec,Curtis Donahue,Rohde a

3、nd Schwarz Samuel Kocsis,Amphenol ICC,Upen Reddy Kareti,Cisco Systems SPEAKERSSpeaker 1 Chris DiMinicoPresident,MC Communications/PHY-SI,LLCcdiminicoieee.org|www.phy-Chris DiMinico is President of MC Communications a telecommunications consulting firm President/CTO of PHY-SI,LLC producing high speed

4、 test fixtures,and co-founder SenTekse developing single-pair Ethernet equipment.Chris has over 30 years of experience in the telecommunication industry and plays an active role in the development of a number of telecommunication industry standardsSpeaker 2 Jason EllisonStaff Signal Integrity Engine

5、er,TE C| Jason J Ellison received his Masters of Science in Electrical Engineering from Penn State University in December 2017.He is employed as a signal integrity engineer and develops high-speed interconnects,lab automation technology,and calibration technology.His interests are signal integrity,p

6、ower integrity and embedded system design.He holds patents related to interconnect technology and has published several articles related to de-embedding and surface roughness.3SPEAKERSSpeaker 3 Alessio AlaimoTechnical Leader Hardware Engineering,CISCO S|Alessio Alaimo is a Technical Leader Engineer

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1. **会议与主题**:2025年1月28-30日圣克拉拉会议中心,主题为200Gb/s/通道测试夹具的插入损耗校正与延迟特性实现。 2. **核心方法**:采用部分去嵌入(partial de-embedding)技术,基于IEEE 370标准校准测试夹具损耗,验证IEEE 802.3ck(100Gb/s)和802.3dj/D1.3(200Gb/s)一致性。 3. **关键数据**: - 参考插入损耗(IL)在53.125 GHz下符合IEEE标准(如Clause 92、162B.2.1)。 - 部分去嵌入后,眼高(EH)和垂直眼闭合(VEC)参数与参考夹具(HCBref)误差小于0.5 dB(表5)。 - 脉冲响应(PFR)的ISI比从实测7.7%降至2.3%-2.9%,接近参考值2.7%(图30-34)。 4. **结论**:部分去嵌入可有效修正测试夹具损耗,避免过/欠均衡导致的误判,适用于高速互连测试。
**测试损耗修正法** 如何在实际200Gb/s测试中有效修正测试夹具的插入损耗? **延迟表征技术** 延迟表征对高速信号测试有何关键影响? **C2M合规验证** 部分去嵌法如何确保C2M测试结果的准确性?
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