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DC25_SLIDES_Track3_NextGeneration224GbpsPAM4Linear_Li.pdf

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1、Information Classification:GeneralWelcome to ConferenceJanuary 2830,2025Santa Clara Convention Center1ExpoJanuary 2930,2025 Information Classification:GeneralNext Generation 224 Gbps-PAM4 Linear:Host TX/RX,Electrical/Optical Channel Characteristics,and End-to-End Link Simulation and AnalysisMike Li(

2、Altera)Hsinho Wu,Masashi Shimanouchi,Itamar Levin,Ariel Cohen(Altera)Edward Frlan,Mark Kimber,Bill Kirkland(Semtech)2Information Classification:GeneralSPEAKERSDr.Mike LiFellow,Altera(An Intel Company)Dr.Peng(Mike)Li is an Altera Fellow and a Chief Technologist for high-speed SERDES,I/O,and interconn

3、ects,covering link technology;standards;SerDes architecture;electrical and optical signaling and interconnects;silicon photonics integration;optical FPGA(OFPGAs);and high-speed simulation,debug and test for jitter,noise,signaling and power integrity,from design,to validation,to high-volume manufactu

4、ring(HVM).3Information Classification:GeneralAgendaIntroductionOIF-CEI-224G-Linear-PAM4 Applications and RequirementsSpecification Methodology Test Point MeasurementsTX/RX Host OIF-CEI-224G-LR-PAM4 Specifications224G-Linear Optical PMD Specifications per IEEE 802.3dj 800GBASE-DR4/1.6TBASE-DR8224G-Li

5、near-PAM4 end-to-end SimulationsConclusions and Next Steps4Information Classification:General5Benefits of Linear Lower power retimed-non-retimed-module power saving Lower latency retimed-non-retimed-lower latency as no ADC/DSP Cost retimed-non-retimed-lower cost as no CDR/ADC/DSP No RetimerNo Retime

6、rHost+Non-retimed LPOHostHost+non-Retimed LPOLPOLPOHostMMF/SMF10m 10 KM Why LPO?Information Classification:GeneralCEI-224G-Linear-PAM4 Applications224G Linear is applicable to both pluggable and NPO/CPO optical systems:6Host TxHost RxDriverTIADriverE/OO/ETx host channelRx Eq.Mod connTx ICRx IC224G L

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1. **会议与主题**:2025年1月28-30日圣克拉拉会议中心,聚焦224Gbps-PAM4线性技术(OIF-CEI-224G-Linear),涵盖主机TX/RX、电气/光通道特性及端到链路仿真分析。 2. **核心优势**:线性方案(非重定时)降低功耗约50%、减少延迟(无ADC/DSP)、降低成本(无CDR/ADC/DSP)。 3. **关键参数**: - 支持波特率72-112 GBd,预-FEC BER≤2×10⁻⁴,主机通道损耗≤16 dB(TP0-TP1a/TP4a-TP5)。 - TP1a提案:EECQ≤3 dB,VMA 250-500 mV;TP4提案:EECQ≤8 dB,过冲≤25%。 4. **仿真与标准**:基于IEEE 802.3dj 800GBASE-DR4/1.6TBASE-DR8,采用Class A/B参考封装,端到端仿真验证BER性能。 5. **下一步**:OIF工作组推进规范草案,结合硬件测量进一步优化。
**224G Linear优势?** (吸引关注技术升级的受众,突出低功耗、低延迟等核心卖点) **TP1a参数如何?** (针对工程师群体,聚焦关键测试点指标,引发技术细节探讨) **LPO为何重要?** (以行业痛点切入,强调无重定时器方案的成本与性能优势)
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