DC25_SLIDES_TRACK10_In-SituSystemLevelPDNMeasurements_Bogatin.pdf

1、Information Classification:GeneralWelcome to ConferenceJanuary 2830,2025Santa Clara Convention Center1ExpoJanuary 2930,2025 Information Classification:GeneralIn-Situ System Level PDN Impedance MeasurementsAdinath Phene,(University of Colorado,Boulder)Dr.Eric Bogatin,(University of Colorado,Boulder)A

2、dinath Phene(University of Colorado,Boulder),Dr.Eric Bogatin(University of Colorado,Boulder)Dr.Melinda Piket-May(University of Colorado,Boulder)Rylee Beach(Electrical Engineer II,BAE Systems)2Information Classification:GeneralImageImage SPEAKERSAdinath PheneGraduate Student,University of Colorado Bo

3、ulderAdinathgirish.phenecolorado.edu|Prof.Eric BogatinProfessor,University of Colorado BoulderEric.bogatincolorado.edu|Home|Eric Bogatin|University of Colorado BoulderTechnical Editor,Signal Integrity JournalFellow,Teledyne LeCroy3Information Classification:GeneralIn-Situ System Level PDN Impedance

4、Measurements4Power-rail-related switching noise on the die is related to the PDN profile as seen by the dieTraditional PDN measurements at the board look at the die through the package in parallel with the board PDNCan we observe the PDN profile from the dies perspective using I/O pins?VRMBulk capsI

5、nterconnectsDecoupling capsPkg and Die Board Die the GPIOInformation Classification:GeneralOutline5 New measurement methodology Test vehicle design Measurement results Hacking the model to create a digital twin Consistency tests So what:Results and InterpretationInformation Classification:General2 P

6、ort Low Impedance Measurement Technique6 Using 2-port shunt method Using Rodhe and Schwarz ZNL20 VNA Noise floor 1 mOhm from 50 kHz to 20 GHz Calibration using ecal unitInformation Classification:GeneralNovel Connections to the GPIO Power Pins7 Power pinsPort 1&Port 2 GPIO pinPort 1 Power pinsPort 1