DC25_SLIDES_Track07_IntrapairSkewElectricalDelayCompensation_Zhang.pdf

1、Information Classification:GeneralWelcome to ConferenceJanuary 2830,2025Santa Clara Convention Center1ExpoJanuary 2930,2025 Information Classification:GeneralIntra-pair Skew Electrical Delay Compensation for PCIe 6.0Kai Xiao,(Intel Corporation)Xinjun Zhang(Intel Corporation),Wenwu Wang(Intel Corpora

2、tion),Kai Xiao(Intel Corporation),Chenghai Yan(Intel Corporation),Weizhe Li(Intel Corporation),Jingbo Li(Intel Corporation),Mo Liu(Intel Corporation),Xiaoning Ye(Intel Corporation)2Information Classification:GeneralSPEAKERS3Kai XiaoPrinciple Engineer,Intel C Kai Xiao is currently a Principal Enginee

3、r in Data Center Group at Intel,responsible for the interconnect solutions for high-speed differential interfaces including PCI Express(PCIe)and Ultra-Path Interconnect(UPI)on Intel Datacenter and Enterprise platforms.Information Classification:GeneralAUTHORSXinjun ZhangTech lead,Intel CKai XiaoPrin

4、ciple Engineer,Intel C4Wenwu WangSI engineer,Intel CChenghai YanSI engineer,Intel CInformation Classification:GeneralAUTHORSWeizhe LiSI engineer,Intel CMo LiuTech lead,Intel C5Jingbo LiTech lead,Intel CXiaoning YeSenior Principal Engineer,Intel CInformation Classification:General Intra-pair skew is

5、common.Running skew:accumulated intra-pair skew as signals travel through a differential pair.Intra-pair Skew in Real PCB Layout690-degree bend generates about 18mil skew(stackup geometry depended)Skew can be compensated by bends in the opposite direction.Maximum intra-pair running skew is about 54

6、mils,Final intra-pair skew is around a maximum of 36 mils.Information Classification:General Source skews are usually generated from pin-field region and main routing region.Structures Generating Source Skew7Pin-field Region(SOC or Conn)Main Routing RegionInformation Classification:General Saw-tooth