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DC25_SLIDES_Track05_InnovativeInterposerSolutionsforHBM_Ilamparidhi_V4.pdf

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1、Information Classification:GeneralWelcome to ConferenceJanuary 2830,2025Santa Clara Convention Center1ExpoJanuary 2930,2025Information Classification:GeneralInnovative Interposer Solutions for HBM3/4:A path to 12.8GbpsIlamparidhi I,(Alphawave Semi)Suriya Prakash T(Alphawave Semi)Gangaraju M(Alphawav

2、e Semi)Yadavalli Jagadeeswari(Alphawave Semi)Diksha Acharya(Alphawave Semi)2Information Classification:GeneralImageSpeaker&AuthorIlamparidhi IPrincipal SI-PI Engineer,Alphawave S3Ilamparidhi I is a Principal SI-PI Engineer at Alphawave Semi with over 19 years of industry expertise in AnalogMixed Sig

3、nal(AMS)System Modelling&Optimization,Advanced Package Design&Optimization,and PCB design.He leads a technical team focused on developing next-generation Die to Die solutions for UCIe and HBM interfaces.He holds an MTech in Microwave and Photonics from the Indian Institute of Technology,Kanpur(IIT-K

4、),and hasworked with leading companies such as Cisco,Seagate,Rambus,Xilinx,and Freescale Semiconductor.In the pastyear,he has driven key innovations at Alphawave Semi,resulting in the filing of 4 US patents(pending approval)related to Advanced package design and Analog Mixed Signal(AMS)system for hi

5、gh-performance HBM and UCIetechnologies.Information Classification:GeneralImageCo-AuthorsSuriya Prakash TGangaraju MGangarajuMisanAdvancedPackageDesignEngineeratAlphawaveSemiwith3+yearsofexpertise in HBM and UCIe.He specializes in layout,3DEM extraction,and innovationsin advancedpackaging,with one U

6、S patent(pending approval).4Yadavalli JagadeeswariYadavalli.JYadavalli Jagadeeswari is an Advanced PackageDesign Engineer at Alphawave Semi with 3+yearsof expertise in HBM and UCIe.She specializes inlayout,3DEMextraction,andinnovationsinadvanced packaging,with one US patent(pendingapproval),and is p

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1. **HBM3/4高速接口挑战**:HBM3接口1024位/16通道,微凸点间距48×55μm,需在380μm宽度内扇出96信号,路由长度约5.1mm;HBM4位宽翻倍至2048位,路由长度增至7.1mm,SI问题加剧。 2. **创新屏蔽设计**:新型Si中介层采用接地笼结构(水平/垂直地线+过孔),降低串扰18dB(VTF-Xtalk@4.2GHz从-16dB至-34dB),但插入损失增加(VTF-IL@4.2GHz从-0.1dB至-1.3dB)。 3. **布局优化方法**:结合2D/3D EM工具优化地线宽度、间距及层间偏移,4层Si中介层支持HBM3@12.8Gbps(眼宽47.27ps),6层有机中介层满足HBM4@12.8Gbps需求。 4. **均衡技术**:HBM4@12.8Gbps面临上升/下降时间退化问题,需采用CTLE+1/2-tap DFE均衡,或放宽眼高要求(如六边形掩模)以减少对均衡的依赖。
HBM3/4如何提速? 互连方案如何优化? 信号干扰如何解决?
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