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DC25_SLIDES_TRACK01_UsingResponseSurfaceMethodology_Neally_v3.pdf

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1、Information Classification:GeneralWelcome to ConferenceJanuary 2830,2025Santa Clara Convention Center1ExpoJanuary 2930,2025 Information Classification:GeneralUsing Response Surface Methodology to Overcome Incumbent Inertia:A T-coil Case StudyScotty Neally(AMD),David Kopp(AMD),Garth Sundberg(Ansys)2I

2、nformation Classification:GeneralImageSPEAKERSScotty NeallyAnalog Design Engineer,AMDScotty Neally received a B.S.E.E from California Polytechnic University,San Luis Obispo.He is an accomplished signal integrity engineer with fifteen years of experience designing and consulting with high density PCB

3、,PKG,and silicon products.Scotty is a subject matter expert in automation of signal integrity flows,and he currently focuses on system design for emerging technologies.David KoppAnalog Design Engineer,AMDDr.David Kopp received a B.S.E.E.from Clarkson University,and a M.S.E.E.and Ph.D.from the Univer

4、sity of Notre Dame,focusing on the electromagnetic design,fabrication,and millimeter wave measurement of novel packaging technologies.He has ten years of experience in the signal integrity field,largely focused on the SerDes design of high speed 802.3 and PCIe,including simulation tool development a

5、nd server design.He is a major contributor to the Statistical Eye Analysis(Seasim)project,which is a standard industry tool for PCIe signoff.3Information Classification:GeneralImageSPEAKERSGarth SundbergSenior Principal Engineer,ADr.Garth Sundberg received a B.S.E.E.and M.S.E.E from Oregon State Uni

6、versity focusing on microwave engineering and compact modeling.Dr.Sundberg earned a Ph.D.in Electrical and Computer Engineering from Portland State University focusing on computational electromagnetics and remote sensing.Dr.Sundberg is a senior member of the IEEE.Dr.Sundberg is a Senior Principal En

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1. **会议与主题**:2025年1月28-30日圣克拉拉会议中心,主题为“利用响应面方法论克服惯性:T-coil案例研究”。 2. **核心问题**:高速设计中,设计复用易导致“惯性”,忽略边界条件变化(如接地布线),影响性能。 3. **解决方案**:采用AI与HPC技术(如Ansys VeloceRF、optiSLangAI)实现闭环优化,直接以眼图开眼率为指标,动态调整T-coil参数(如层数、线宽)。 4. **关键数据**: - 优化后眼图高度Pareto前沿呈凸形,读写性能存在强权衡; - 计算资源需求随设计阶段激增(如最终阶段需80核并行,耗时133小时)。 5. **结论**:AI驱动设计可突破传统局限,提升高速互连性能与适应性。
**AI如何优化设计?** **T-coil设计难点?** **如何克服惯性设计?**
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