DC25_SLIDES_Track07_SolvingAKeySignalIntegrityBottleneck_Liu.pdf

1、Information Classification:GeneralWelcome to ConferenceJanuary 2830,2025Santa Clara Convention Center1ExpoJanuary 2930,2025Information Classification:GeneralSolving a Key Signal Integrity Bottleneck Issue to Continue Scaling PCIe 7.0 over Copper ChannelsMo Liu,Ph.D.Carolina Garcia Robles,Intel Corp.

2、Kai Xiao,Intel Corp.Kuan-yu Chen,Intel Corp.2Information Classification:GeneralImageSPEAKERSMo LMo Liu was a Technical Lead with Intel.She joined AMD recently.3Kai Xiao,Ph.D.Principle Engineer,Intel C Kai Xiao is currently a Principal Engineer in Data Center Group at Intel,responsible forthe interco

3、nnect solutions for high-speed differential interfaces including PCI Express(PCIe)and Ultra-Path Interconnect(UPI)on Intel Datacenter and Enterprise platforms.Information Classification:GeneralSPEAKERSCarolina Garcia Robles Intel CCarolina is a signal integrity engineer in the Intel Data Center and

4、AI group.She is involved in modelingand analysis of high-speed differential signaling channels.Carolina joined Intel in 2011.She received theB.S degree in electronics from the Instituto Tecnologico de Puebla,Mexico,in 2008,and the M.S.degree in electronics from the Instituto Nacional de Astrofisica,

5、Optica y Electronica(INAOE),Puebla,Mexico in 2012.Kuan-yu Chen Intel CorporationKuan- Kuan-Yu Chen,who joined Intel in 2011,is a signal integrity engineer in the Intel Data Center and AI group.He is involved in modeling and analysis of high-speed differential signaling as well as DDR channels.Kuan-Y

6、u received the M.S.degree in electronical engineering from the Syracuse University,New York,in 2002.4Information Classification:GeneralPCIe Technology Trend50501001502002503002000 2002 2004 2006 2008 2010 2012 2014 2016 2018 2020 2022 2024 2026 2028 2030Data Rate Per Diferential PairYearPCIe Data Ra