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DC25_SLIDES_Track06_PanelPCIExpressAndPAM4_Alavi.pdf

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1、Information Classification:GeneralWelcome to ConferenceJanuary 2830,2025Santa Clara Convention Center1ExpoJanuary 2930,2025 Information Classification:GeneralPCI Express&PAM4:Balancing Silicon and interconnect interdependencies for 128 GT/s Panel DiscussionPegah Alavi(Keysight Technologies),Steve Kr

2、ooswyk(Samtec),Sam Kocsis(Amphenol)Rick Eads(Keysight Technologies),David Bouse(Bitifeye),Madhumita Sanyal(Synopsys Inc)2Information Classification:GeneralSpeakersPegah AlaviSenior Solutions EngineerKeysight TechnologiesPegah is a Senior Applications Engineer at Keysight Technologies,where she focus

3、es on Signal Integrity and High Speed Digital Systems and Applications.Prior to joining Keysight Technologies,Pegah worked on system level modeling of analog and mixed signal circuits in order to best predict the overall systems performance and accurately represent each component.Steve KrooswykNew P

4、roduct and Standards SISamtecSteve is involved in new high-speed connector development and PCIe standards at Samtec.His 20 years of signal integrity experience has had a focus on the design,simulation,and correlation of PCIe interconnect and I/O.Previously,Steve was the PCIe tech lead for SI in Inte

5、ls data center division during Gen3 and Gen4 development.He is an author of the book High Speed Digital Design:Design of High Speed Interconnects and Signaling and holds a MS degree from the University of South Carolina.3Information Classification:GeneralSpeakersSam KocsisDirector of Standards and T

6、echnologyAmphenolSam Kocsis currently holds the role of Director of Standards and Technology at Amphenol,focusing on the proliferation of innovative interconnect solutions.Sam coordinates Amphenols engagement strategies in various industry standards and consortiums across networking,server/storage,o

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1. **会议与主题**:2025年1月28-30日圣克拉拉会议中心,聚焦PCI Express & PAM4技术,探讨128 GT/s(PCIe 7.0)的硅与互连依赖平衡。 2. **PCIe 7.0核心参数**:128 GT/s PAM4,BER 1e-6(前FEC),SNDR 34dB,RLM 0.95,通道损失-36dB至-40dB@32GHz。 3. **技术挑战**:多电平信噪比降低、眼宽不对称、功耗增加,需统计与逐位仿真结合。 4. **测量与仿真**:需65GHz示波器,支持SER、眼图、抖动测试,IBIS-AMI模型及端到端仿真。 5. **光学扩展**:光学PCIe兼容铜缆,需Retimer,预算~9dB@16GHz,复用SFF-TA-1032等接口。 6. **AI/ML应用**:128G SerDes支持AI集群扩展,加速器、交换机等互连,预研BER达1e-9。
PCIe 7.0如何实现128GT/s? 光学PCIe有何突破? 128G SerDes如何支撑AI?
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