DC25_PAPER_Track9_LowLatencySpeculativeErrorCorrection_Nir_V10.pdf

1、 Information Classification:General Low latency speculative error correction using simplified ML detector for 64Gbps wireline transceiver Ehud Nir,Mansi Mehrotra,Amin Karami,Chris Holdenried,Robert Wang Cadence Design Systems,Toronto,Canada Information Classification:General Abstract Wireline interc

2、onnect data-rates have been doubling consistently every 3-4 years due to increasing demand for higher connectivity speed in datacenters.With limited improvement of the electrical channels,MLSE has emerged as a key digital technique for boosting signal power in wireline links,at the price of increase

3、d latency and die area.This paper presents an ultra-low latency speculative error correction(SEC)engine embedded within the DFE.It uses a simplified ML detector to correct single symbol errors before they propagate into a burst.Significant reduction of the trellis size is achieved by using soft info

4、rmation together with assumptions on the error distribution.The design was customized for an existing Gen6 PCIe PHY in 5nm CMOS technology.Simulated and measured SNR gain exhibits comparable performance at a fraction of the latency and area of full MLSE.Authors Biography Ehud Nir Ehud Nir received t

5、he B.Sc.and M.Sc.degrees in Electronics Engineering from Tel Aviv University,Tel Aviv,Israel,in 2001 and 2013,respectively.He has over 25 years of experience in custom digital and DSP circuit design.He is currently a director of digital engineering at Cadence Design Systems Inc.,developing high-spee

6、d digital circuits for wireline communication.Mansi Mehrotra Mansi Mehrotra received the Bachelor of Engineering degree in Electronics Engineering from Indian Institute of Technology,BHU(IIT BHU),India,in 2012.She has over 11 years of experience in digital design of Controllers and PHY Subsystems.Sh