DC25_PAPER_Track5_OffChipDesignMethodFor_Park_V2.pdf

1、 Information Classification:General Off-Chip Design Method for Improving Signal Integrity in Multi Branch Parallel interface of Non-Volatile Memory Jiwoon Park,Samsung Electronics Sujin Kim,Samsung Electronics Soyoung Jung,Samsung Electronics Kwangsoo Park,Samsung Electronics Jihyung Jung,Samsung El

2、ectronics Juhwan Lim,Samsung Electronics Jaesang Yun,Samsung Electronics Youngmin Ku,Samsung Electronics Sunghoon Chun,Samsung Electronics Information Classification:General Abstract Solid State Drives(SSDs)with high performance and high capacity have become more essential for AI/cloud server storag

3、e.Low power signaling and termination techniques like Low Tapped Termination(LTT)or Power Isolated Low Tapped Termination(PI-LTT)are required for parallel interfaces between the SSD controller and Non-Volatile Memory(NVM)as toggle 6.0 supports high-speed up to 4.8 Gbps.Thus,this paper presents a nov

4、el off-chip design solution for reducing signal and power noise by high-loading and multi branch topologies.Reflection and crosstalk are analyzed as well as power noise for multi branch topology of SSD Printed Circuit Board(PCB).And this paper proposes the Reflection-Controlled Branch(RCB)method whi

5、ch improves eye opening by 43%by controlling reflection timing and optimizing channel branch ratio.In addition,practical channel optimization method using reinforcement learning is proposed for finding optimal On-Die Termination(ODT)termination.The proposed RCB method is validated by both measuremen

6、t and simulation.Author(s)Biography Jiwoon Park received the B.S degree in information and communication engineering from Inha University,Incheon,South Korea,in 2006 and the M.S degree in electrical engineering from the Korea Advanced Institute of Science and Technology(KAIST),Daejeon,South Korea,in