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DC25_PAPER_Track13 Beyond200GBrickwallsOf400G_dePaulis_v2.pdf

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1、 Information Classification:General Beyond 200G:Brick Walls of 400G links per Lane Brandon Gore,Samtec Corporation Brandon.G Andrew Josephson,Samtec Corporation Andrew.J Richard Mellitz,Samtec Corporation Richard.M Francesco de Paulis,University of LAquila francesco.depaulisunivaq.it Information Cla

2、ssification:General Luis Boluna,Keysight Technologies John Calvin,Keysight Technologies Rick Rabinovich,Keysight Technologies Mike Resso,Keysight Technologies mike_ Information Classification:General Abstract Data rate demands beyond 200 Gb/s PAM4 per lane are emerging from new applications such as

3、Artificial Intelligence(AI)and machine learning(ML).Artificial intelligence high performance computing clusters have significantly impacted the physical infrastructure requirements of data center facilities.As the demand for data processing and storage continues to surge,these data centers are grapp

4、ling with the challenge of evolving and expanding exponentially to keep pace with growth.The changing landscape of platforms,equipment design,architecture topologies,power density requirements,and cooling demands all underscore the pressing need for new architectural designs.Physical layer performan

5、ce of the network data center must be improved by meeting many design challenges included but not limited to minimizing insertion loss and eliminating reflections while controlling the impedance environment throughout all copper interconnects.Moving to 400 Gb/s per lane requires a progression of mat

6、erials,interconnects,and manufacturing methods as well as new system topologies.This paper will explore these challenges and propose practical engineering solutions to fulfill the predicted 400 Gb/s per lane goals necessary for AI/ML large language learning models.Author(s)Biography Brandon T.Gore i

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1. **400G/424G PAM4需求**:AI/ML集群推动数据中心单通道速率达400G PAM4(Nyquist频率106.25GHz),需解决物理层设计挑战。 2. **关键瓶颈**: - **连接器谐振**:QSFP/OSFP连接器弹簧与PCB微带指的"擦拭尾"(wipe tail)形成λ/4谐振(如0.3mm长在ε_eff=2.2时谐振于106GHz),导致插入损耗滚降。 - **辐射与串扰**:PCB走线(如125μm宽在80GHz呈λ/16偶极辐射)和地槽(如80GHz槽径向辐射)在高频下效率提升,加剧串扰。 - **阻抗失配**:表面贴装AC耦合组件在424G PAM4下插入损耗达10dB(远超212G的0.6dB)。 3. **替代方案**: - **共封装设计**:采用HDI/SLP基板集成硅芯片与双轴电缆,实现100GHz线性插入损耗。 - **高阶调制**:PAM6(225GBd)可支持424G,但需更高SNR( slicer SNR增加3.6dB)。 4. **结论**:传统PCB拓扑无法满足400G+需求,需新架构(如正交板级设计)和调制技术突破。
**400G信号瓶颈?** **AI集群的带宽挑战?** **PCB设计如何突破?**
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