DC25_PAPER_Track1_ReducingChipsRespinRateBy _Zamek_V2.pdf

1、 DesignCon 2025 Reducing Chips Respin Rate by Fixing Common Decoupling Methods Flaws Iliya Zamek Abstract A recent survey indicates that bringing a new chip to market typically requires 2 to 7 chip re-tape outs and more for HPC and AI/ML processors.Analysis shows that many chip respins may be caused

2、 by high voltage variations and decay on the Power rail of the chip die.On-die voltage and current transients are challenging to measure or simulate,so they are often not thoroughly examined during the product design phase.These noises reveal themselves at product validation as chip failures.Unstudi

3、ed,these chip failures could not easily be explained and may often be misinterpreted as chip flaws necessitating chip respins.It was revealed that common decoupling methods and PDN guidance may worsen these transients instead of reducing them.Simulations with developed PDN tools illustrate a huge va

4、lue of transients hidden inside the chip.This work demonstrates that improving the decoupling methods and PDN guidance could prevent and reduce costly chip respins.Author(s)Biography Dr.Iliya Zamek has many years of broad scientific and hands-on engineering experience and has held various engineerin

5、g and management roles in Product Engineering and NPI,including ATE&Test station design,HW Architecture,R&D,SOC post-silicon validation,and development of electrical and Opto-electrical products.He held multiple engineering roles in Q-Tech,Altera,Semtech,and Inphi,and on contracts for Intel,Microsof

6、t,and other Corp.,doing design and development of XO,PLL and CDR,FPGA,ASIC,post-silicon validation of 40G,100/400G Transceivers and Serdes,SOC,and AI/ML processors.Hes done extensive research on Power-induced Jitter and Power Integrity methodology.Since 2006 he has been a member of the DesignCon Tec