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DC25_SLIDES_Drive_DegassingHolesInBGAPackage_Occhiali_V2.pdf

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1、Information Classification:GeneralDegassing Holes in BGA Package Design:Prediction of Impact on Power Integrity Using SimulationMarco Occhiali,Ansys ItalyMarco Occhiali,Georgios Korompilis(Ansys)Aurora Sanna,Cristina Somma,Damian Halicki,Simona Cucchi(STMicroelectronics)12025 ANSYS,Inc.Context and I

2、ntroduction32025 ANSYS,Inc.Used in laminate package technology to allow the outflow of gas generated during manufacturing preventing copper delaminationVoids applied on large continuous copper shapes(power and ground planes exceeding a certain size)Specific design rulesVariable size and shape(circle

3、,square,oval)Variable pitch(within min and max values)variable densityDegassing Holes:Basics42025 ANSYS,Inc.Prevention of copper delamination Easier copper balancing between opposite layers,thanks to the variable density of holesPros Signal integrity degradation:voids in reference ground planes can

4、affect the signals return path Power integrity degradation:copper removal from power and ground planes can increase power supply impedance(higher inductance,higher resistance,lower capacitance)and create current bottlenecksMitigated by keeping a degassing-free area below/above the most critical sign

5、al tracesDegassing Holes:Pros And ConsConsFocus of this work:PI performance verified on 3 different test casesComparison through RLC analysis,impedance analysis,time-domain PI analysissubstrate coreSignal layer:low Cu percentagePlane layer:degassing helps Cu balancing52025 ANSYS,Inc.Test Cases Descr

6、iption 2 power planes 40 mm2 each Ground planes on multiple layers(variable size)Variable degassing pitch(density)on each layer,depending on Cu-balancing needsTest case 2Test case 1Test case 3 1 power plane,8 mm2 area Ground planes on multiple layers(variable size)Variable degassing pitch(density)on

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1. **作用与影响**:BGA封装中排气孔用于防止铜分层,但会减少电源/地平面铜面积(测试案例1-3减少2%-5%),导致电阻(DCR)增加1%-8%,电感(L)在高频下变化更显著(-7%)。 2. **性能分析**: - **封装级**:全PDN阻抗变化微小(<1%),单引脚阻抗局部增加最高50%(位置相关); - **系统级**:阻抗和时域电压(如Vpk-pk)差异可忽略。 3. **仿真成本**:排气孔使全波仿真时间增加100%(如案例1从15分钟增至28分钟),但精度提升有限。 4. **结论**:排气孔对电源完整性(PI)影响通常较小,除非对极敏感应用或局部效应关注,否则无需额外仿真开销。
**BGA排孔影响?** **排孔设计利弊?** **排孔模拟耗时?**
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