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DC25_PAPER_Track6_DirectToSubstrate200GPAM4_Krooswyk.pdf

上传人: S** 编号:1240793 2026-05-16 14页 1.26MB

1、 Information Classification:General Direct to Substrate 200G-PAM4 Co-Packaged Connectors:Is it a Reality?Steve Krooswyk,Samtec Jignesh Shah,Samtec Evan Beauprez,Broadcom Regee Petaja,Broadcom Information Classification:General Abstract Co-packaged connectors(CPC)and cables can avoid the loss and ref

2、lections from the packageboard interface and increase system reach.But why havent they taken off?Apparent SI advantages are not everything-assembly and process must be refined.Enablers for direct to substrate connectivity are reviewed including package stiffeners,separable interface,solder attachmen

3、t,and aggressive miniaturization.Results include package after reflow,VNA and BER measurements of full channels with CPC.Author(s)Biography Steve is technical lead in Samtecs high speed connector and cable development group.His 20 years of experience includes a role as PCI Express lead in Intels Dat

4、a Center Group,introducing excursion metrics in the PCI-SIG,co-authoring High Speed Digital Design for High Speed Interconnects&Signaling,and an MS from U.of South Carolina.Jignesh Shah is a Technologist in Samtecs High Speed Connectivity group.He has over 25 years of experience in the architecture

5、and design of both copper and optical interconnects.Jignesh has engineering degrees from UT Austin and IIT Bombay.Evan is technical lead in Broadcoms Signal Integrity group within the companys ASIC Product Division.With 19 years of experience,his roles have included high speed SerDes design,system a

6、rchitecture and signal integrity.Evan holds a BS in Computer Engineering from Colorado State University.Regee Petaja is the APD System Signal Integrity Manager at Broadcom.Currently working on 100+Gbps SerDes system design,debug and support.Information Classification:General Introduction The next ge

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1. **CPC优势**:共封装连接器(CPC)通过避免封装/PCB接口的损耗和反射,提升系统带宽和传输距离,支持224G-PAM4高速信号,可扩展至2米铜缆传输。 2. **关键性能**:实测通道插入损耗约22dB(53GHz),误码率(BER)低至3.3e-9;近端串扰(NEXT)<-60dB(40GHz内),远端串扰(FEXT)约-49dB。 3. **密度与设计**:采用0.4-0.5mm针距,支持1024对差分信号,封装尺寸<100×100mm;通过强屏蔽抑制串扰,优化焊盘长度减少反射。 4. **组装工艺**:优先焊贴连接器(二次回流),避免压缩接口的散热和可靠性问题;需重新设计封装加强板并验证热性能。 5. **应用场景**:替代传统PCB布线和近芯片布线(NCC),解决长距离I/O路由限制,减少有源器件需求。
**CPC技术优势?** **如何实现高密度连接?** **CPC组装挑战?**
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