DC25_PAPER_Track14_AcceleratingChipletPlacementAndRouting_HaeyeonKim_V2.pdf

1、 Information Classification:General Accelerating Chiplet Placement and Routing Optimization with Machine Learning Haeyeon Rachel Kim,KAIST haeyeonkimkaist.ac.kr Federico Berto,KAIST fbertokaist.ac.kr Junghyun Lee,KAIST Hyunjun An,KAIST Taein Shin,KAIST Chuanbo Hua,KAIST Jinkyoo Park,KAIST Youngwoo K

2、im,Sejong University Joungho Kim,KAIST Information Classification:General Abstract Chiplet technology has emerged as a promising solution to address the growing demand for improved system performance and customization while maintaining production cost efficiency.Chiplet-based systems offer several k

3、ey economic advantages over monolithic chips,including im proved wafer yield,mixed process technology node integration,reduced time to market,and the ability to overcome reticle size limitations.However,the heterogeneous integration of an increas ing number of chiplets and their interconnections pos

4、es a significant challenge in chiplet placement and routing.Chiplet placement is subject to various hard constraints,such as physical limitations,signal integrity,power integrity,and thermal coupling considerations,making it a complex problem distinct from traditional chip placement.In this paper,we

5、 formulate the chiplet placement and routing problem as a constrained combinatorial optimization task and propose a novel representation and benchmark for this problem.To overcome the challenges associated with reinforcement learning,such as extensive exploration and high computational costs,we empl

6、oy imitation learning,which offers faster and more stable training.We train autoregressive policies using expert data generated by our novel Place-to-Route heuristic algorithm,which effectively combines rule-based strategies with iterative optimization to produce high-quality solutions while ensurin