DC25_PAPER_Track06_DesignShiftLeftEnablingEarly_Halupka.pdf

1、 Information Classification:General Design Shift-Left:Enabling Early Digital Design and HDL Generation via SerDes System Model David Halupka,SeriaLink Systems L Marc Erickson,The MathWorks,I Aleksey Tyshchenko,SeriaLink Systems Ltd.Johnathan Adams,The MathWorks,Inc.Barry Katz,The MathWorks,Inc.Infor

2、mation Classification:General Abstract High-speed mixed-signal systems,such as 112+Gb/s SerDes,often use analog and digital subsystems with complex interactions.The increasing performance requirements for these systems and manufacturing variation drive increased system and digital/analog interaction

3、 complexity.More complex interactions lead to longer design cycles and a higher probability of overlooked design issues.This paper shows how synthesizable-HDL digital-hardware algorithms were developed,validated,refined,and automatically generated from within a high-level SerDes system modeling envi

4、ronment.We use this flow to demonstrate the design of a decision feedback equalizer(DFE)adaptation algorithm.This algorithm is then refined into a bit-and sample-time accurate hardware algorithm,which is automatically exportable into a synthesizable hardware-description language(HDL).The DFE adaptat

5、ion algorithm is fully developed using a high-level language.It starts as a sample-time and hardware-independent algorithm and then is converted into a sample-time and hardware-accurate algorithm,leveraging the system model for end-to-end link validation and design verification.This workflow decreas

6、ed design time by allowing interacting subsystems to be designed and validated in parallel.It builds on our published series of validation and design shift-left enabling flows,where we showed how to automatically generate and use mixed-signal behavioral models for digital verification and design.Aut