DC25_PAPER_Track10_InSituSystemLevelPDN_Bogatin.pdf

1、 1|P a g e In situ System Level PDN Impedance Measurements.Adinath Phene,University of Colorado,Boulder Adinathgirish.phenecolorado.edu Eric Bogatin,University of Colorado,Boulder Eric.bogatincolorado.edu Rylee Beech,BAE Systems rylee.beachcolorado.edu Melinda Piket-May,University of Colorado,Boulde

2、r melinda.piket-maycolorado.edu 2|P a g e Abstract Designing a power distribution network from the die to the VRM is increasingly important in all electronic systems as noise margins decrease,current draws increase and switching times decrease,all driven by lower cost.The importance of this problem

3、has stimulated advances in refining best system-level design practices,simulation tools that enable exploring virtual prototypes of PDN systems,and measurement methods to measure ultra-low impedance PDN elements below 1 mOhm impedances at GHz frequencies.Most of the measurement methods implemented h

4、ave focused on component characterization or board-level PDN measurements.What is really important is being able to measure and validate the PDN impedance profile of the PDN system,from the die,looking outward all the way to the VRM,while the chip is powered on.The methods reported to perform in sit

5、u PDN measurements use either special test chips or expensive probe stations that are difficult to use with large or complex boards.This paper introduces a simple method to measure the system-level PDN impedance profile from the dies perspective,including the on-die capacitance all the way to the VR

6、M.It is suitable for sub-milliOhm impedances and in the GHz frequency range in a powered or unpowered state.This technique leverages the commonly used 2-port shunt VNA method,applied to using two independent package-lead connections to the chip.Three special features enable this method to be applied