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DC25_SLIDES_Track01_FastDesignAndSimulationOf_Dai_V2.pdf

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1、Information Classification:GeneralWelcome to ConferenceJanuary 2830,2025Santa Clara Convention Center1ExpoJanuary 2930,2025Information Classification:GeneralFast Design and Simulation of Photonic Computing Chip with Chiplet-based Heterogeneous IntegrationMingyang Jiang(Lightstandard),Xuanjiang Shen(

2、Lightstandard)2Wenliang Dai(Xpeedic)Information Classification:GeneralSPEAKERSWenliang DaiPresident,XWenliang Dai is Co-Founder,President of Xpeedic.He received the M.S.degreein electromagnetic fields and microwave technology from University Of ElectronicScienceAndTechnologyOfChina(UESTC)andthePh.D.

3、degreeinelectromagnetic fields and microwave technology from Shanghai Jiao TongUniversity(SJTU),Shanghai,China,in 2001 and 2004,respectively.Dr.Dai is aConsultant of MIIT National IT talent development project.He was a SeniorMember of Consulting Staff at Cadence Shanghai R&D Center.He was a regularr

4、eviewer for international journals and conferences including IEEE TMTT,IEEETAP,DAC,etc.3Information Classification:GeneralOutline4 Background Introduction of Photonic Computing Chip:Principle of Photonic Computing ChipPhotonic Computing Chip Structure Design of Photonic Computing Chip Based on 2.5D

5、Silicon Interposer:High Performance Design ProcessLayout and Physical Implementation 2.5D Interposer SI/PI Simulation:Pre/Post SI SimulationDC IR-drop Simulation SummaryInformation Classification:GeneralBackground of Photonic Computing 5Training FLOPS for Transformer models has been growing at a rat

6、e of 750 x/2yrsPhotonicsElectronicsImprovementLatency100ps100ns103Bandwidth20GHz2GHz10Power1uW1mW103Area2500um22500um21Hardware FLOPS,memory,and interconnect bandwidth have been increasing falling behind.Photonic computing has the potential to overcome these challenges.Information Classification:Gen

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1. **会议信息**:2025年1月28-30日于圣克拉拉会议中心举办,主题为“基于Chiplet异构集成的光子计算芯片快速设计与仿真”。 2. **光子计算优势**:相比电子计算,光子计算在延迟(100ps vs 100ns)、带宽(20GHz vs 2GHz)和功耗(1μW vs 1mW)上显著提升,可解决Transformer模型训练算力增长(750x/2年)带来的硬件瓶颈。 3. **芯片架构**:采用2.5D硅中介层集成20余个Chiplet,通过高密度互连(xDAC/wDAC)和TSV供电,利用相变材料(PCM)实现非易失性光学计算。 4. **设计挑战**:多芯片异构集成需解决I/O凸块阵列设计、自动布线(高速差分对/电源网格)及跨尺度SI/PI仿真(如12.5Gbps SerDes信号眼图分析、12电源域IR-drop≤8.3mV)。 5. **工具流程**:基于Synopsys 3DIC Compiler,结合Xpeedic EM/Spice仿真工具,实现从预布局SI优化到后布局PI验证的全流程。
光子计算芯片优势? 2.5D设计挑战? SI/PI仿真关键?
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