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DC25_PAPER_Track3_DevelopmentOfACoPackagedApplication_XU_V2.pdf

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1、 Information Classification:General Development of a co-packaged Application Specific IC with direct drive optical engine chiplets Qing Xu,Ranovus Inc.QingR Jeff Hutchins,Ranovus Inc.JeffR Bin Cao,Omid Jafari,Georg Roell,Hojjat Salemi,Hamid Arabzadeh Ranovus Inc.Chih-Yi Kuan,Yu-Cheng Hsu,Chih-Wei Su

2、ng MediaTek Inc.Bono Liao,Brad Hsu,Mark Lin Foxconn Interconnect Technology Information Classification:General Abstract This paper presents the development of a co-packaged multi-chip module(MCM)that integrates an ASIC with 6.4T Silicon Photonics Micro-Ring Modulator-based optical engine(OE)chiplets

3、.Two versions of the OE are discussed:one that incorporates on-chip laser sources and another that supports external light sources.The paper covers system considerations,signal integrity analysis,co-simulation,optimizations,and mechanical and thermal modeling.Additionally,it explores the design meth

4、odology and trade-offs involved in achieving MCM integration of the ASIC and optical engines on a single substrate.This approach is being further developed to support 200G signaling rates,paving the way for I/O capacities exceeding 100 Tbps in future compute engines.Information Classification:Genera

5、l Author(s)Biography Qing Xu holds a BSEE degree from Shanghai Jiao Tong University,a Master Ingnieur degree from ESME Paris,and a Ph.D.in Electrical Engineering from Tlcom Paris(ENST).He joined RANOVUS Inc.in 2017,where he currently serves as Senior Technical Leader of Application Engineering.Qing

6、has also held various roles at Belden and Ericsson.He is the author of over 30 conference and technical papers and holds six granted U.S.patents.His current research focuses on monolithic integrated photonics transceivers,with an emphasis on close integration and co-optimization with high-speed SerD

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1. **技术方案**:开发集成ASIC与6.4T硅光微环调制器光学引擎(OE)芯片的多芯片模块(MCM),支持112G-PAM4-LR SerDes,总带宽14.4Tbps(6.4Tbps通过CPO,其余通过可插拔模块)。 2. **核心优势**:CPO方案显著降低功耗(Odin®8P-ELS为3.9pJ/bit,ILS为4.5pJ/bit,较传统模块节省3-4.6倍),提升能效与密度,支持AI计算集群低延迟需求。 3. **系统设计**:采用8×Odin®8P OE(4×集成激光ILS,4×外置激光ELS),通过LGA插座与 substrate 互联,热仿真确保OE温度<70℃(45℃环境)。 4. **性能验证**:端到端BER达2E-10至2E-8(PRBS31Q),兼容800G-DR8模块及OIF ELSFP标准,支持200G演进(目标100-200Tbps I/O)。
**CPO如何提升能效?** **200G光引擎有何突破?** **光引擎如何实现集成?**
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